DC1041A-B Linear Technology, DC1041A-B Datasheet - Page 7

• Manufacturer Part Number: DC1041A-B
• Description: BOARD DEMO LTM4601HV
• Manufacturer: Linear Technology
• Series: µModuler

Specifications of DC1041A-B

• Design Resources: LTM4601HV Spice Model LTM4601 Gerber Files DC1041 Design File DC1041 Schematic
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: 0.6V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, or 5V
• Current - Output: 12A
• Voltage - Input: 4.5 ~ 28 V
• Regulator Topology: Buck
• Frequency - Switching: 800kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LTM4601HV
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN FUNCTIONS
V
tween these pins and PGND pins. Recommend placing
input decoupling capacitance directly between V
and PGND pins.
V
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. Review the fi gure below.
PGND (Bank 2): Power ground pins for both input and
output returns.
V
This pin connects to the ground remote sense point. The
remote sense amplifi er is used for V
V
This pin connects to the output remote sense point. The
remote sense amplifi er is used for V
DIFFV
fi er. This pin connects to the V
DRV
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure
18. This improves effi ciency at the higher input voltages
by reducing power dissipation in the module.
INTV
the 5V internal regulator.
OSNS
IN
OUT
OSNS
(Bank 1): Power Input Pins. Apply input voltage be-
CC
CC
(Bank 3): Power Output Pins. Apply output load
–
+
OUT
(Pin M12): (–) Input to the Remote Sense Amplifi er.
(Pin E12): This pin normally connects to INTV
(Pin J12): (+) Input to the Remote Sense Amplifi er.
(Pin A7): This pin is for additional decoupling of
(Pin K12): Output of the Remote Sense Ampli-
(See Package Description for Pin Assignment)
OUT_LCL
OUT
OUT
pin.
BANK 1
BANK 2
BANK 3
PGND
≤3.3V.
≤3.3V.
V
OUT
V
IN
M
D
G
H
A
B
C
E
K
L
F
J
1 2 3 4 5 6 7
IN
pins
CC
TOP VIEW
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock above 2V and
below INTV
TRACK/SS (Pin A9): Output Voltage Tracking and Soft-
Start Pin. When the module is confi gured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to the ground,
and connecting the center point of the divider to this pin.
See Applications Information.
MPGM (Pin A12): Programmable Margining Input. A re-
sistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kΩ will equal a
value in millivolts that is a percentage of the 0.6V refer-
ence voltage. See Applications Information. To parallel
LTM4601HVs, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
f
external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See Applications Information for fre-
quency adjustment.
V
Internally, this pin is connected to V
60.4k precision resistor. Different output voltages can be
programmed with an additional resistor between V
SGND pins. See Applications Information.
SET
FB
8 9 10 11 12
(Pin F12): The Negative Input of the Error Amplifi er.
(Pin B12): Frequency Set Internally to 850kHz. An
CC
f
MARG0
MARG1
DRV
V
PGOOD
SGND
V
DIFFV
V
V
SET
FB
OSNS
OUT_LCL
OSNS
. See Applications Information.
CC
OUT
+
–
LTM4601HV
OUT_LCL
pin with a
FB
4601hvfa
and
7