MC33560DTBR2G ON Semiconductor, MC33560DTBR2G Datasheet - Page 16

• Manufacturer Part Number: MC33560DTBR2G
• Description: IC INTERFACE PWR MANAGMT 24TSSOP
• Manufacturer: ON Semiconductor

Specifications of MC33560DTBR2G

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 24-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC33560DTBR2GOS

requires to supply to the card (ICCmax, on the y−axis)
level. The curve is associated with an inductance value
(22 mH, 47 mH, or 100 mH).
level to find the R
filtering capacitor is generally charged before inductance
current reaches current limitation, while for alow inductance
value, the current limitation is activated after a few converter
cycles.
R
supply is shown by the curves in Figures 6 and 7.
special care has to be taken to extend its lifetime. When
lithium batteries approach the end−of−life, their internal
resistance increases, while voltage decreases. This
phenomenon can prevent the startup of the DC−DC
converter if the current limiting is set too high, because of the
filtering capacitor charging current.
CLOCK GENERATOR
match the smartcard operating frequency to the system
frequency. The source frequency can be provided to
ASYCLKIN by the microcontroller itself or from an
external oscillator circuit.
low) the three input variables PWRON, I/O and RESET are
used to configure the two output variables CRDV
CRDCLK as described in Table 3. This circuit setup is
latched during the positive transition of CS.
frequency ASYCLKIN can be divided by a factor of 1, 2
or 4. The circuit controls the frequency commutation to
guarantee that the card clock signal remains free from spikes
and glitches. In addition, this circuit ensures that CRDCLK
signal pulses will not be shorter than the shortest and/or
longer than the longest of the clock signals present before
and after programming changes.
lim
First, determine the maximum current that the application
Then, select one curve that crosses the selected ICC
Finally, use the intersection of the curve and the ICCmax
Good starting values are : L1 = 47 mH; R
Note also that, for a high inductance value (100 mH), the
Battery Requirements: Having determined the L
When the application is powered by a single 3.0 V battery,
The primary purpose of the clock generator module is to
In programming mode (RDYMOD=L and CS asserted
Furthermore, in asynchronous mode the system clock
values, the maximum current drawn from the battery
lim
value on the x−axis.
ASYCLKIN
SYNCLK
INVOUT
RESET
IO
Figure 23. Clock Generator Functional Block
CARDENABLE
lim
= 0.5 W
B
2
LATCH
CC
http://onsemi.com
1
B
and
and
max
2
MC33560
16
SELECTOR
PROGRAM
LATCH
without additional load to the microprocessor quartz
oscillator. It can also be used to build a local RC oscillator.
This driver has been optimized for low consumption; it has
no hysteresis, and input levels are not symmetrical. If the
ASYCLKIN pin is connected to a sine wave, the duty cycle
will not always be 50% at INVOUT.
CLOCK GENERATOR OPERATING PRINCIPLES
memory cards. It can also be used for asynchronous
(microprocessor) cards, allowing the use of two different
clock sources. The status of SYNCLK is latched at
CRDCLK when CS goes high, so that data (the I/O pin) and
clock are always consistent at the card connector, whatever
the CS status is. When using the synchronous clock, the
clock output becomes active only when the MC33560 is
selected with CS
microprocessor cards. When applied, the clock output
remains active even when the MC33560 is not selected with
CS, in order to keep the microprocessor running and avoid
an unwanted reset. The ASYCLKIN signal is buffered at the
INVOUT pin, so that several MC33560 systems can use the
same clock with one load only.
or divided by 2 or by 4 to the CRDCLK pin. If the duty cycle
of the applied clock signal is not exactly symmetrical, it is
recommended that the clock signal be divided by two or four
to guarantee 50% duty cycle.
(Figure 29). The clock divider includes synchronization
logic that controls the switch from synchronous clock to
asynchronous (and vice−versa), from any division ratio to
any other ratio, during CS changes and at powerup. The
synchronization logic guarantees that each clock cycle on
the CRDCLK pin is finished before changing clock
selection (and has always the adequate duration), regardless
of the moment the programming is changed.
signal at the CRDCLK pin has an entire length, according
to the selected divide ratio, whatever the ASYCLKIN signal
is versus the internal sequencer timing.
The INVOUT output is provided to drive other circuits
Synchronous Clock: This clock is used mainly for
Asynchronous Clock: This clock is used mainly for
Depending on programming, the frequency is fed directly,
Clock Signal Synchronization and Consistency
At powerup, when ASYCLKIN is selected, the clock
SYNCHRO
LATCH
SEQ3
.
CRDVCC
CRDCLK