PI74SSTU32864ANBE Pericom Semiconductor, PI74SSTU32864ANBE Datasheet

PI74SSTU32864ANBE

Manufacturer Part Number

PI74SSTU32864ANBE

Description

IC 25BIT CONFIG REG BUFF 96LFBGA

Manufacturer

Pericom Semiconductor

Datasheet

1.PI74SSTU32864ANBE.pdf (10 pages)

Specifications of PI74SSTU32864ANBE

Applications

DDR2 RDIMM

Interface

Differential

Voltage - Supply

1.7 V ~ 1.9 V

Package / Case

96-LFBGA

Mounting Type

Surface Mount

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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BOSTOCK HK LIMITED

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PI74SSTU32864ANBE

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Pericom

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Part Number:

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Features

• PI74SSTU32864A is designed for low-voltage operation,

• Supports Low Power Standby Operation

• Enhanced Signal Integrity for 1 and 2 Rank Modules

• All Inputs are SSTL_18 Compatible, except RST, C0, C1,

• Output drivers are optimized to drive DDR2 DIMM loads

• Designed for DDR2 Memory

• Packaging (Pb-free & Green available):

Block Diagram 1:2 Mode (Positive Logic)

which are LVCMOS.

-96 Ball LFBGA (NB)

DCKE

DODT

DCS

CSR

RST

REF

= 1.8V

TO OTHER CHANNELS

Note: Disabled in 1:1 configuration

QCKEB*

QODTB*

QCSB*

QCKEA

QODTA

QCSA

Q1B*

Q1A

Description

Pericom Semiconductor’s PI74SSTU32864A logic circuit is

produced using advanced CMOS technology. This 25-Bit 1:1 or

14-Bit 1:2 configurable registered buffer is designed for 1.7V to

1.9V V

All clock and data inputs are compatible with the JEDEC standard

for SSTL_18. The control inputs are LVCMOS. All outputs are

1.8V LVCMOS drivers that have been optimized to drive the

DDR2 DIMM load.

The SSTU32864A operates from a differential clock (CK and

CK). Data is registered at the crossing of CK going high, and CK

going low.

The C0 input controls the pinout configuration of the 1:2 pinout

from A configuration (when LOW) to B configuration (when

HIGH). The C1 input controls the pinout configuration for 25-Bit

1:1 (when LOW) to 14-Bit 1:2 (when HIGH).

The device supports low-power standby operation. When the reset

input (RST) is low, the differential input receivers are disabled and

undriven (floating) data, clock and reference voltage (V

are allowed. In addition , when RST is low, all registers are reset,

and all outputs are forced low. The LVCMOS RST and Cn inputs

must always be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has

been supplied, RST must be held in the low state during power up.

In the DDR-II RDIMM application, RST is specified to be completely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

reset, the register will be cleared and the outputs will be driven

low quickly, relative to the time to disable the differential input

receivers. However, when coming out of reset, the register will

become active quickly, relative to the time to enable the differential

input receivers.

As long as the data inputs are low, and the clock is stable during

the time from the low-to-high transition of RST until the input

receivers are fully enabled, the design of the SSTU32864A must

ensure that the outputs remain low, thus ensuring no glitches on

the output.

The device monitors both DCS and CSR inputs and will gate the

Qn outputs from changing states when both DCS and CSR inputs

are high. If either DCS or CSR input is low, the Qn outputs will

function normally. The RST input has priority over the DCS and CSR

control will force the outputs low. If the DCS control functionality

is not desired, then the CSR input can be hardwired to ground,

in which case, the set-up time requirement for DCS would be the

same as for the other D data inputs.

25-Bit 1:1 or 14-Bit 1:2 Configurable

operation.

PI74SSTU32864A

Registered Buffer

PS8743

REF

) inputs

08/02/04

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PI74SSTU32864ANBE Summary of contents

Page 1

... Note: Disabled in 1:1 configuration TO OTHER CHANNELS Description Pericom Semiconductor’s PI74SSTU32864A logic circuit is produced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1. All clock and data inputs are compatible with the JEDEC standard for SSTL_18 ...

Page 2

Pin Configuration 1:1 Register ( DCKE NC V REF B D2 D15 GND C D3 D16 DODT NC GND E D5 D17 D18 GND ...

Page 3

Pin Configuration 1:2 Register ( REF GND GND GND ...

Page 4

Terminal Functions Name GND Ground V Power Supply DD V Input Reference Voltage REF Z Reserved for future use OH Z Reserved for future use OL CK Positive master clock input CK Negative master clock input C0, C1 Configuration control ...

Page 5

Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................................... –65°C to +150°C Supply Voltage Range, V .............................................–0.5V to 2.5V DD Input Voltage Range,V : (See Notes 2 and 3): ................–0.5V to ...

Page 6

Electrical Characteristics Over Recommended Operating Free Air Temperature range Parameters Description All inputs I Static Stand- Static Operating Dynamic Operating Clock only Dynamic Operating - per each data input, 1:1 mode I DDD ...

Page 7

Switching Characteristics Over Recommended Operating Free Air Temperature range (See Figure 1) Parameters f max t pdm tpdmss (1, 2) (simultaneous switching) t RPHL Note: 1. Includes 350ps test load transmission-line delay. 2. This parameter is not necessarily production tested. ...

Page 8

Test Circuit and Switching Waveforms CK Inputs 100-ohm LVCMOS RST Input t inact I DD (2) 10% Voltage and Current Waveforms Input Active and Inactive Times t w Input V ICR Voltage Waveforms - ...

Page 9

Load Circuit -High -to- Low Slew Rate Measurement Voltage Waveforms - Low -to- High Slew Rate Measurement Figure 2. Output Slew-Rate Measurement Information (V Notes includes probe and jig capacitance L 2. All input pulses are supplied by ...

Page 10

... Packaging Mechanical: 96-ball LFBGA (NB) Ordering Information Ordering Code PI74SSTU32864ANB PI74SSTU32864ANBE Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. Number of Transistors = TBD Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com Package Code NB 96-Ball LFBGA NB Pb-free & Green, 96-Ball LFBGA 10 PI74SSTU32864A 25-Bit 1:1 or 14-Bit 1:2 ...

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