W83637HG-AW Nuvoton Technology Corporation of America, W83637HG-AW Datasheet
W83637HG-AW
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W83637HG-AW Summary of contents
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... Winbond LPC I/O W83637HF W83637HG Revision: 1.6 Date: 2006/03/22 ...
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PAGES DATES 03/25/2001 2 08/09/2001 3 02/18/2002 4 08/28/2002 5 09/27/2002 7 6 04/15/2003 100~101 7 130~137 06/25/2003 8 N.A. 11/23/2005 9 N.A. 02/10/2006 10 Page.5 03/23/2006 Please note that all data and specifications are subject to ...
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Tables of Contents- 1. GENERAL DESCRIPTION...................................................................................................... 1 2. FEATURES............................................................................................................................. 3 3. BLOCK DIAGRAM .................................................................................................................. 7 4. PIN CONFIGURATION ........................................................................................................... 8 5. PIN DESCRIPTION................................................................................................................. 9 5.1 LPC Interface ............................................................................................. 10 5.2 FDC Interface ............................................................................................. 11 5.3 Multi-Mode Parallel Port ............................................................................. 12 ...
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SMI# Interrupt Mode ................................................................................... 34 6.6.1 Voltage SMI# mode.....................................................................................................34 6.6.2 Fan SMI# mode...........................................................................................................34 6.6.3 The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes ........35 6.6.4 The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI# interrupt has two modes ...
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Logical Device A (ACPI) ............................................................................118 8.5 Logical Device B (Hardware Monitor).........................................................126 8.6 Logical Device C (Smart Card interface) ....................................................126 8.7 Logical Device D (MS/SD Card Interface) ..................................................127 9. ELECTRICAL CHARACTERISTICS .....................................................................................129 9.1 Absolute Maximum Ratings .......................................................................129 9.2 DC Characteristics.....................................................................................129 ...
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GENERAL DESCRIPTION W83637HF/HG is the new generation of Winbond's LPC I/O products evolving product from Winbond’s most popular LPC I/O chip W83627HF/HG – which integrates the disk driver adapter, serial port (UART), keyboard controller (KBC), SIR, ...
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W83637HF/HG provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O port. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. ...
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FEATURES General • Meet LPC Spec. 1.01 • Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) • Compliant with Microsoft PC2000/PC2001 Hardware Design Guide • Support DPM (Device Power Management), ACPI • Programmable configuration settings • Single MHz ...
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Infrared • Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps • Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps • Support Consumer IR Parallel Port • Compatible with IBM parallel ...
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General Purpose I/O Ports • 21 programmable general purpose I/O ports • General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, KBC control I/O pins, suspend ...
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Automatic Power On voltage detection Beep • Issue SMI#, IRQ, OVT# to activate system protection • Winbond Hardware Doctor TM • Intel LDCM / Acer ADM Package • 128-pin PQFP TM Support TM compatible - 6 - W83637HF/HG Publication ...
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BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock Hardware monitor channel and Vref Memory Stick Card interface signals LPC Interface Game FDC Port MIDI URA, B GPIO ...
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PIN CONFIGURATION ...
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PIN DESCRIPTION I/O12t TTL level bi-directional pin with 12 mA source-sink capability. I/O24t TTL level bi-directional pin with 24 mA source-sink capability. I/O12ts TTL level Schmitt-trigger bi-directional pin with 12 mA source-sink capability. I/O24ts TTL level Schmitt-trigger bi-directional pin ...
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LPC Interface SYMBOL PIN I/O CLKIN PME 12t PCICLK LDRQ 12t SERIRQ 23 I/O 12t I/O LAD[3:0] 24-27 12t LFRAME LRESET FUNCTION System ...
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FDC Interface SYMBOL PIN I/O DRVDEN0 1 OD 24t INDEX csu MOA 24t DSB 24t I/O FANIN3 24ts DSA 24t MOB 24t OD FANPWM3 24t DIR 24t ...
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FDC Interface, continued SYMBOL PIN I/O DSKCHG csu 5.3 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL PIN I/O SLCT WE2# OD 12t ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O ACK DSB2# OD 12t PD7 35 I/O 12ts DSA2# OD 12t PD6 36 I/O 12ts MOA2# OD 12t PD5 37 I/O 12ts FUNCTION PRINTER MODE: ACK# An active low input ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD4 38 I/O 12ts DSKCHG2 PD3 39 I/O 12ts RDATA2 PD2 40 I/O 12ts WP2 PD1 41 I/O 12ts TRAK02 FUNCTION PRINTER MODE: PD4 Parallel ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD0 42 I/O 12ts INDEX2 SLIN 12t STEP2# OD 12t INIT 12t DIR2# OD 12t FUNCTION PRINTER MODE: PD0 Parallel port data bus bit 0. parallel port ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O ERR HEAD2# OD 12t AFD 12t DRVDEN0 OD 12t STB 12t FUNCTION PRINTER MODE: ERR# An active low input on this pin indicates that the printer ...
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Serial Port Interface SYMBOL PIN I/O CTSA CTSB# 78 DSRA DSRB# 79 RTSA HEFRAS cd RTSB ENGMTO cd DTRA PNPCVS cd ...
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Serial Port Interface, continued SYMBOL PIN I/O DTRB SINA SINB 82 SOUTA PENKBC cd SOUTB PEN48 cd DCDA DCDB# 84 RIA ...
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ACPI Interface SYMBOL PIN PSOUT 12t PSIN VBAT 74 pvdf_rc1000_vbat 5.7 Hardware Monitor Interface SYMBOL PIN I/O CASEOPEN VIN2 97 AIN VIN1 99 AIN CPUVCORE 100 AIN VREF 101 AOUT VTIN ...
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Game Port & MIDI Port SYMBOL PIN I/O MSI 119 INtu GP20 I/OD MSO 120 O 8c IRQIN0 INc GPSA2 121 Incsu GP17 I/OD 12csu GPSB2 122 Incsu GP16 I/OD 12csu GPY1 123 I/OD 12csd I/OD GP15 GPY2 124 ...
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Card Reader Interface 5.9.1 Smart Card Interface SYMBOL PIN I/O SCRWLED 2 OD 24t SMI# OD 24t IRQIN IN t GP27 I/OD 24t SCPWCTL# 106 O 24t SCRST# 107 O 24t SCIO 108 I/O 24t SCPSNT 109 IN ts ...
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General Purpose I/O Port 5.10.1 General Purpose I/O Port 1 (Power source is Vcc) see 1.8 Game Port 5.10.2 General Purpose I/O Port 2 (Power source is Vcc) SYMBOL PIN I/O IRTX 87 O 12t GP26 I/OD 12t IRRX ...
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Power Pins SYMBOL PIN VCC 12, 48, 77 VSB 61 VCC3V 28 +3.3VIN 98 +5VIN 114 CPUD- 111 VSS 20, 55, 86, 117 FUNCTION +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. ...
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HARDWARE MONITOR 6.1 General Description W83637HF/HG can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and ...
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LPC Bus Port 5h Index Register Port 6h Data Register Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h Serial Bus Address 48h Monitor Value Registers 20h~3Fh ...
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Analog Inputs The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage, ...
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Monitor over 4.096V voltage The +12V input voltage can be expressed as following equation. The value of R1 and R2 can be selected to 28K Ohms and 10K Ohms, respectively, when the input voltage V1 is 12V. The node ...
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Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor SYSTIN and 9-bit two's-complement for sensor CPUTIN and VTIN. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained ...
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FAN Speed Count and FAN Speed Control 6.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not ...
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Divisor Nominal PRM 1 8800 2 (default) 4400 4 2200 8 1100 16 550 32 275 64 137 128 68 Time per Counts Revolution 6.82 ms 153 13.64 ms 153 27.27 ms 153 54.54 ms 153 109.08 ms 153 218.16 ...
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Fan speed control The W83637HF provides maximum 3 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 Index 01h, Index 03h and Index 11h. ...
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Smart Fan Control Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. 6.5.1 Thermal Cruise mode There are maximum 3 pairs of Temperature/FanPWM control at this mode: SYSTIN with ...
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Tolerance Target Temperature Tolerance One more protection is provided that duty cycle will not be decreased the above (3) situation in order to keep the fans running with a minimum speed. By setting CR[12h] bit3 ...
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Manual Control Mode Smart Fan control system can be disabled and the fan speed control algorithem can be progrmmed by BIOS or application software. The programming method is just as section 6.4.2. 6.6 SMI# Interrupt Mode The SMI#/OVT# pin ...
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The W83637HF temperature sensor 1(SYSTIN) SMI# interrupt has two modes (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127°C will set temperature sensor 1 SMI# to HYST the Comparator Interrupt Mode. Temperature exceeds T interrupt and ...
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The W83637HF temperature sensor 2(CPUTIN) and sensor 3(VTIN) SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode Temperature exceeding T Interrupt Status Register. Once an interrupt event has occurred by exceeding ...
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OVT# Interrupt Mode The SMI#/OVT# pin (pin105 multi-function pin. The function is selected at Configuration Register CR[28h] bit 6. The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index52h bit1and Bank2 Index52h bit1. (1) Comparator ...
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Registers and RAM Address Port and Data Port are set in the register CR60 and CR61 of Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For ...
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Configuration Register Index 40h Register Location: Power on Default Value Attribute: Size Bit 7: A one restores power on default value to all registers except the Serial Bus Address register. This bit clears itself ...
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Interrupt Status Register 1 Index 41h Register Location: Power on Default Value Attribute: Size: Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit ...
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Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan Bit 6: A one indicates that the SYSTIN temperature has been over ...
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SMI# Mask Register 2 Index 44h Register Location: Power on Default Value Attribute: Size: Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. Reserved Register Index 45h Chassis ...
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Fan Divisor Register I Index 47h Register Location: 47h Power on Default Value: 5Fh Attribute: Read/Write Size: 8 bits 7 Bit 7-6: FAN2 Divisor bit1:0 . Bit 5-4: FAN1 Divisor bit1:0. Bit 3-0: CPU Vcore ID ...
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Value RAM Index 20h- 3Fh Address A6-A0 20h VCORE reading 21h VIN1 reading 22h +3.3VIN reading 23h +5VIN reading 24h VIN2 reading 25h Reserved 26h Reserved 27h SYSTIN temperature sensor reading 28h FAN1 reading Note: This ...
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Value RAM Index 20h- 3Fh, continued Address A6-A0 36h Reserved 37h Reserved 38h Reserved 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit 3Bh FAN1 Fan Count Limit Note the number of counts of ...
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Fan Divisor Register II - Index 4Bh Register Location: Power on Default Value Attribute: Size: 7 Bit 7-6:Fan3 speed divisor. Please refer to Bank0 CR[5Dh] , Fan divisor table. Bit 5-4: Select A/D Converter Clock Input. <5:4> ...
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SMI#/OVT# Control Register- Index 4Ch Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Reserved. User Defined. Bit 6: Set to 1, the SMI# output type of Temperature CPUTIN/VTIN is set to Comparator Interrupt mode. Set to 0, ...
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FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: Power on Default Value Attribute: Size: 7 Bit 7~6: Reserved. Bit 5: FAN 3 output value if FANINC3 sets to 0. Write 1, pin5 (DSB#/FANIN3) generates a logic high signal. ...
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Register 50h ~ 5Fh Bank Select Register - Index 4Eh Register Location: Power on Default Value Attribute: Size: 7 Bit 7: HBACS- High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh ...
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BEEP Control Register 1-- Index 56h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: BEEP output control for FAN 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, ...
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BEEP Control Register 2-- Index 57h (Bank 0) Register Location: 57h Power on Default Value 80h Attribute: Read/Write Size: 8 bits 7 Bit 7: Global BEEP Control. Write 1, enable global BEEP output. Default 1. Write 0, disable all BEEP ...
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Reserved Register -- Index 59h (Bank 0) Register Location: Power on Default Value Attribute: Size: Bit 7: Reserved Bit 6: Diode mode selection of temperature VTIN if index 5Dh bit3 is 1. Set this bit to 1, select Pentium II ...
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VBAT Monitor Control Register -- Index 5Dh (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Fan3 divisor Bit2. Bit 6: Fan2 divisor Bit2. Bit 5: Fan1 divisor Bit2. Bit 4: Reserved. Bit 3: Sensor type ...
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Reserved Register -- 5Eh (Bank 0) Reserved Register -- 5Fh (Bank 0) CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h(Bank1) Register Location: 50h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <8:1> of CPUTIN sensor, which ...
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CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) Register Location: Power on Default Value Size: 7 Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before ...
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CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. CPUTIN Temperature Sensor Over-temperature (High Byte) ...
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CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. VTIN Temperature Sensor Temperature (High Byte) Register ...
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VTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Register Location: 51h Attribute: Read Only Size: 8 bits 7 Bit 7: Temperature <0> of sensor3, which is low byte, means 0.5 Bit 6-0: Reserved. VTIN Temperature Sensor ...
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VTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. VTIN Temperature Sensor ...
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VTIN Temperature Sensor Over-temperature (High Byte)Register - Index 55 (Bank 2) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. VTIN Temperature Sensor Over-temperature (Low ...
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Interrupt Status Register 3 -- Index 50h (BANK4) Register Location: Power on Default Value Attribute: Size: Bit 7-3: Reserved. Bit 2: A one indicates that the VTIN temperature has been over the target temperature for 3 minutes with full fan ...
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Reserved Register -- Index 52h (Bank 4) BEEP Control Register 3-- Index 53h (Bank 4) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always ...
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Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value ...
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Register Location: Power on Default Value Attribute: Size: 7 Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Bit 6: FAN 1 ...
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Register Location: Power on Default Value Attribute: Size: Bit 7: Smart Fan 2 warning status. Set 1, the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan temperature ...
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Register Location: Power on Default Value Attribute: Size: 7 Bit 7-2: Reserved. Bit 2: Smart Fan 3 warning status. Set 1, the VTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise ...
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Value RAM 2 Index 50h - 5Ah (auto-increment) (BANK 5) Address A6-A0 Auto-Increment 50h Reserved 51h VBAT reading. The reading is meaningless if EN_VBAT_MNT bit(CR5D bit0) is not set. 52h Reserved 53h Reserved 54h Reserved 55h Reserved ...
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FANPWM1 Duty Cycle Select Register-- 01h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: FANPWM1 duty cycle control. Write FF, duty cycle is 100%. Write 00, duty cycle is 0%. FANPWM2 Output Frequency Configuration Register—Index02h ...
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FANPWM2 Duty Cycle Select Register-- 03h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7-0: FANPWM2 duty cycle control. Write FF, duty cycle is 100%. Write 00, duty cycle is 0%. FAN Configuration Register I -- ...
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Set 10, FANPWM1 is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 1: FANPWM2 output mode selection. Set to 0, FANPWM2 pin is as output pin so that it can drive a logical high or low ...
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CPUTIN Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h (Bank 0) Register Location: Power on Default Value Attribute: Size (1). When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: CPUTIN Target Temperature. (2). When at ...
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FANPWM1 Stop Duty Cycle Register -- Index 08h (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM1 duty cycle will decreases to below this value. This register ...
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FANPWM1 Start-up Duty Cycle Register -- Index 0Ah (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM1 duty cycle will increase from 0 to this register value to provide a ...
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FANPWM1 Stop Time Register -- Index 0Ch (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, this register determines the time of which FANPWM1 duty is from stop duty cycle to 0 ...
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Fan PWM Duty Cycle Step Down Time Register -- Index 0Eh (Bank 0) Register Location: Power on Default Value Attribute: Size This register determines the speed of FAN PWM decreasing the duty cycle in Smart Fan ...
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FANPWM3 Output Frequency Configuration Register—Index10h (Bank 0) Register Location: Power on Default Value Attribute: Size: 7 Bit 7: FANPWM3 Clock Source Select. This bit selects the clock source of FANPWM3 output frequency. Set to 0, select 24 MHz. Set to ...
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Register Location: Power on Default Value Attribute: Size: 7 Bit7-6: Reserved Bit 5: Set 1, FANPWM1 duty cycle will decrease to and keep the value set in Index 08h when temperature goes below target range. This is to maintain the ...
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VTIN Target Temperature Register/ Fan 3 Target Speed Register -- Index 13h (Bank0) Register Location: Power on Default Value Attribute: Size (1).When at Thermal Cruise mode: Bit7: Reserved. Bit6-0: VTIN Target Temperature. (2).When at Fan Speed Cruise ...
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FANPWM3 Stop Duty Cycle Register -- Index 15h (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, FANPWM3 duty cycle will decreases to below this value. This register ...
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FANPWM3 Stop Time Register -- Index 17h (Bank 0) Register Location: Power on Default Value Attribute: Size When at Thermal Cruise mode, this register determines the time of which FANPWM3 duty is from stop duty cycle to 0 ...
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Reserved -- Index 19h (Bank 0) User Defined Register -- Index 1A- 1Bh (Bank 0) Register Location: Power on Default Value Attribute: Size: Bit 7-0: User can write any value into these bits and read. Reserved -- Index 1Ch-1Fh (Bank ...
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Register File Complete register file table Register file Abbr. Receiver Buffer Base + 0 RBR Register (Read BDLAB = 0 only) Transmitter Buffer Base + 0 TBR Register (Write BDLAB = 0 only) Interrupt Enable Base + 1 Register ...
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Note: Abbreviation explanation (in alphabetical order) – BDLAB – Baud rate divisor latch access bit. CLKSTP – Stop Smart Card interface's clock SCCLK. CLKSTPL – Set SCCLK level when CLKSTP is "1". EPE – Even parity enable. ERDRI – Enable ...
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Receiver Buffer Register (RBR at base address + 0 when BDLAB = 0, read only) This register is the access port for receiver FIFO active when Smart Card interface is in input mode with SCIODIR (bit 1 of ...
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Interrupt Enable Register (IER at base address + 1 when BDLAB = 0) This register includes four control bits to enable interrupt events. The other four bits are allocated for control of general-purpose I/O pins which are usually connected to ...
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Bit 2: ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error, no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above will trigger an interrupt if this bit is ...
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Bit 7, 6: FIFO enabled status bits reflect what is set in bit 0 of SCFR (write only Smart Card FIFO Register at base address + 2 when BDLAB = 0). Bit 5: SCPSNT line status. User may poll this ...
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Smart Card FIFO control Register (SCFR at base address + 2 when BDLAB = 0, write only) This register controls FIFO function of Smart Card interface Bit 7, 6: RxTL1 and RxTL0 mean receiver FIFO active threshold level ...
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Smart Card Control Register (SCCR at base address + 3) In contrast to its UART counterpart, Smart Card Control Register only controls parity bit setting because data length is fixed at 8-bit long for Smart Card interface protocol ...
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Clock Base Register (CBR at base address + 4, default 0Ch) This register combining with BLH and BLL (baud rate latches) determine internal sampling clock frequency. For example, CBR defaults to be 0Ch and BLH, BLL default to be 1Fh ...
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Bit 4: SBD means silent byte detected. This bit is set to "1" to indicate that received data byte are kept in silent state for a full byte time, including start bit, data bits, parity bit, and stop bits. In ...
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Extended Control Register (ECR at base address + 7, default 12h) This register contains reset control bits, clock frequency selection bits, clock stop control bits and SCIO direction control bit Bit 7: Cold reset. Setting "1" to this ...
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Bit 0: Warm reset. Setting "1" to this bit pulls down SCRST#. SCCLK is stopped, SCIO in input mode and SCLED is inactive. ECR's SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are ...
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Smart Card ID Number (base address + 2 when BDLAB = 1, fixed at 70h) This register contains a specific value of 70h for driver to identify Smart Card interface. 7.4 Functional Description The following description uses abbreviations to ...
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To meet another timing requirement ISO/IEC 7816-3, a counter based on SCCLK is implemented to start counting on the rising edge of SCRST#. SCPWR# is deactivated if no ATR (Answer To Reset) is detected after 65536 clock cycles ...
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Power States W83637HF/HG employs a sophisticated algorithm to partition Smart Card interface's internal circuits to achieve optimal power utilization. However, users must pay extra care in the design of application circuits following guidelines stated below to prevent potential signal ...
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Power Down State Transition from active state to power down state is accomplished by setting SCPWD to "1". Clock is stopped for most internal core circuits except detection circuit for SCPSNT toggle (card insertion/extraction). SCPWD could be reset by ...
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CONFIGURATION REGISTER 8.1 Plug and Play Configuration W83637HF/HG uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83637HF/HG, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with ...
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After Power-on reset, the value on RTSA# (pin 43) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an ...
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First, write the Logical Device Number (i.e., 0x07) to the EFIR and then write the number of the desired logical device to the EFDR. If accessing the Chip (Global) Control Registers, this step is not required. Secondly, write the address ...
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The PNP ID of the W83637HF/HG Card Reader Device (For BIOS Programming use) SC (smart card reader) MS (memory stick reader) 8.3 Chip (Global) Control Register CR02 (Default 0x00) Bit Reserved. Bit 0 : SWRST ...
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CR23 (Default 0x00) Bit Reserved. Bit 0 : IPD (Immediate Power Down). down mode immediately. CR24 (Default 0b1s000s0s) Bit 7 : EN16SA = 0 12 bit Address Qualification = 1 16 bit Address Qualification Bit 6 ...
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CR26 (Default 0b0s000000) Bit 7 : SEL4FDD = 0 Select two FDD mode Select four FDD mode. Bit 6 : HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is NRTSA (pin ...
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CR28 (Default 0x00) Bit 7 : PIN5S and PIN7S = 0 pin5 and pin 7 is selected FDC(DSB and MOS) function = 1 pin5 and pin 7 is selected FAN3(FANIN3 and FANPWM3) function Bit 6 : PIN105S = 0 pin105 ...
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CR2A (GPIO multiplexed pin selection register 1. VCC powered. Default 0X7C) Bit 7 : Port Select (select Game Port or General Purpose I/O Port Game Port = 1 General Purpose I/O Port 1 pin121~128 select function GP10~GP17 ...
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CR2B(GPIO multiplexed pin selection register 2. VCC powered. Default 0XC0), continued Bit 3 : PIN88S = 0 IRRX = 1 GP25 Bit 2 : PIN87S = 0 IRTX = 1 GP26 Bit 1-0 :PIN SCLED ...
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CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit Reserved. Bit These bits select DRQ resource for FDC. = 0x00 DMA0 = 0x01 DMA1 = 0x02 DMA2 = ...
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CRF1 (Default 0x00) Bit Boot Floppy = 00 FDD FDD FDD FDD D Bit Media ID1, Media ID0. These bits will be reflected on ...
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CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. TABLE A Drive Rate Table Select DRTS1 DRTS0 DRATE1 TABLE B DTYPE0 ...
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Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60, CR ...
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Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60, CR ...
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CRF0 (Default 0x00) Bit Reserved. Bit 3 : RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode Reception delays 4 characters-time (40 bit-time) when SIR is changed ...
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Bit 2 : HDUPLX. IR half/full duplex function select The IR function is Full Duplex The IR function is Half Duplex. Bit 1 : TX2INV = 0 The SOUTB pin of UART B function or IRTX ...
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CRF0 (Default 0x80) Bit KBC clock rate selection = 00 Select 6 MHz as KBC clock input Select 8 MHz as KBC clock input Select 12 MHz as KBC clock input. = ...
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CR62 (Default 0x03, 0x30 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the MIDI Port base address [0x100:0xFFF byte boundary. CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 ...
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CRF3 (Default 0x00) Bit These bits select IRQ resource for IRQIN1. Bit These bits select IRQ resource for IRQIN0. CRF4 (Reserved) CRF5 (PLED mode register. Default 0x00) Bit 7-6 : select PLED ...
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CRF7 (Default 0x00) Bit 7 : Mouse interrupt reset Enable or Disable = 1 Watch Dog Timer is reset upon a Mouse interrupt = 0 Watch Dog Timer is not affected by Mouse interrupt Bit 6 : Keyboard interrupt reset ...
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Logical Device A (ACPI) (The CR30, 70, F0~F9 are VCC power source; CR E0~E7 are VRTC power source) CR30 (Default 0x00) Bit Reserved. Bit Activates the logical device Logical device ...
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Bit 1 : MSXKEY. This bit combining with MSRKEY (bit 4 of CRE0 of logical device A) and ENMDAT_UP (bit 7 of CRE6 of logical device A) define what kind of mouse wake-up event can trigger an active low pulse ...
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CRE4 (Default 0x00) Bit 7 : Power loss control bit Disable ACPI resume 1 = Enable ACPI resume Bit 6-5 : Power loss control bit <1:0> System always turn off when come back from power ...
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CRE6 (Default 0x00), continued Bit6 : EN_SCUP. Enable SCPSNT# of Smart Card interface to wake up system through PSOUT Disable Enable. Bit CIR Baud Rate Divisor. The clock base of CIR is ...
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CRF0 (Default 0x00) Bit 7 : CHIPPME. Chip level auto power management enable Disable the auto power management functions = 1 Enable the auto power management functions. Bit 6 : CIRPME. Consumer IR port auto power management enable. ...
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CRF3 (Default 0x00) Bit Device's IRQ status. These bits indicate the IRQ status of the individual device respectively. The device's IRQ status bit is set by their source device and is cleared by writing a 1. ...
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CRF6 (Default 0x00) Bit Enable bits of the SMI / PME generation due to the device's IRQ. These bits enable the generation of an SMI / PME interrupt due to any IRQ of the devices. SMI ...
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CRF7 (Default 0x00) Bit 7 : Reserved. Return zero when read Bit Enable bits of the SMI / PME generation due to the GPIO IRQ function or device's IRQ. Bit 6 : SCIRQEN Disable ...
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CRF9 (Default 0x00) Bit Reserved. Return zero when read. Bit 2 : PME_EN: Select the power management events to be either an PME or SMI interrupt for the IRQ events. Note that: this bit is valid ...
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CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ channel for Smart Card interface. CRF0 (Default 0x00) Bit Reserved. Bit 0 SCPSNT_POL (Smart Card Present Polarity). SCPSNT ...
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CRF0 (Default 0x01) Bit Reserved. Bit 2 : SDDET Polarity Select = 1 Active High = 0 Active Low Bit 1 : External SD Card Detect Pin(SDDET; Pin 69) Enable = 1 Enable = 0 Disable ...
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ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage (5V) Input Voltage RTC Battery Voltage V BAT Operating Temperature Storage Temperature Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and ...
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DC Characteristics, continued PARAMETER I/O - TTL level bi-directional pin with 24mA source-sink capability 24t Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage I/O – 3.3V TTL level bi-directional pin ...
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DC Characteristics, continued PARAMETER I/O – 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability 24tsp3 Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage I/OD - ...
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DC Characteristics, continued PARAMETER I/OD - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink 24ts capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage I/OD - ...
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DC Characteristics, continued PARAMETER I/OD - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and 12 csd open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High ...
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DC Characteristics, continued PARAMETER O - Output pin with 24mA source-sink capability 24 Output Low Voltage Output High Voltage O - 3.3V output pin with 12mA source-sink capability 12p3 Output Low Voltage O - 3.3V output pin with 24mA source-sink ...
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DC Characteristics, continued PARAMETER IN - TTL level input pin with internal pull up resistor tu Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage IN - TTL level Schmitt-trigger input pin ts Input Low Threshold Voltage ...
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DC Characteristics, continued PARAMETER IN - CMOS level Schmitt-trigger input pin cs Input Low Threshold Voltage Hystersis Input High Leakage Input Low Leakage IN - CMOS level Schmitt-trigger input pin with internal pull up resistor csu Input Low Threshold Voltage ...
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... ORDERING INSTRUCTION PART NO. W83637HF-AW W83637HG-AW KBC FIRMWARE TM AMIKEY-2 TM AMIKEY-2 - 137 - W83637HF/HG REMARKS Publication Release Date: March, 2006 Revision 1.6 ...
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... Example: The top marking of W83637HG-AW S MART @ W83637HG-AW AM. MEGA. 87-96 109G5BASC 1st line: Winbond logo and S 2nd line: part number: W83637HG-AW; G means Pb-free package 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code IO IO logo MART@ 109 ...
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G : assembly house ID; A means ASE, S means SPIL, G means GR, etc Winbond internal use revision; A means version A, B means version B ...
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PACKAGE DIMENSIONS (128-pin QFP 102 65 103 128 See Detail F y Seating Plane Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Taipei Office ...
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APPENDIX A: APPLICATION CIRCUITS WDTO PLED MS5 MS3 CPUD I MSCLK MS4 MS2 Use 627HF remove MS1 parts R2,R4 AVCC Use 637HF remove R3 0 parts R1,R3 VIN2 R4 0 IO3V R6 VIN1 H/W ...
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OnNow or Wake_up function power BATTERY CIRCUIT BT1 BATTERY 3V JP5:1-2 Clear CMOS 2-3 Enable ONNOW functions GAME & MIDI PORT CIRCUIT IO5V R21 2.2K MSI GPSA2 GPSB2 R22 2.2K GPY1 R23 2.2K GPY2 R24 2.2K MSO R25 2.2K GPX2 ...
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COM PORT IO5V IO+12V VCC +12V RTSA NRTSA RTSA# DA1 DY1 DTRA NDTRA DTRA# DA2 DY2 SOUTA 13 8 NSOUTA SOUTA DA3 DY3 RIA NRIA RIA# RY1 RA1 CTSA ...
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PRT PORT RP1 2.7K RP5 1 8 STB AFD INIT SLIN# PD[0..7] 22 PD[0..7] RP6 PD0 1 8 PD1 2 7 PD2 3 6 PD3 RP7 PD4 1 8 PD5 2 ...
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PWM Circuit for FAN speed control +12V R37 4.7K Q2 R39 1K PNP 3906 D6 R41 4.7K C45 Q4 JP8 R45 + R44 100 MOSFET N FANPWM1 3 10u 2N7002 2 27K 1 HEADER 3 Temperature Sensing RT1 VREF R48 ...
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SUSPEND LED CIRCUIT D7 Q6 R60 150 2N3904 IOVSB SUSLED R61 4.7K SUSLED POWER LED CIRCUIT D8 Q7 R62 150 2N3904 IO5V LED R63 4.7K PLED PANEL SWITCH JP9 R64 10K IOVSB 1 PSIN 2 HEADER 2 R65 10K C47 ...