W83977ATG-AW Nuvoton Technology Corporation of America, W83977ATG-AW Datasheet
W83977ATG-AW
Specifications of W83977ATG-AW
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W83977ATG-AW Summary of contents
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... W83977ATF W83977ATG WINBOND I/O ...
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... W83977ATF/W83977ATG VERSION VERSION ON WEB 0.50 First published. 0.51 Register correction 0.52 A1 Typo correction and data calibrated spec. revision; configuration register 0.53 A2 programming method. 0.54 A3 Modify ordering information and top marking. ...
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... Universal Asynchronous Receiver/Transmitter (UART A, UART B)................................... 41 6.2 Register Address................................................................................................................. 41 6.2.1 UART Control Register (UCR) (Read/Write) ........................................................................41 6.2.2 UART Status Register (USR) (Read/Write) ..........................................................................43 6.2.3 Handshake Control Register (HCR) (Read/Write) ................................................................44 6.2.4 Handshake Status Register (HSR) (Read/Write)..................................................................45 6.2.5 UART FIFO Control Register (UFR) (Write only)..................................................................46 W83977ATF/W83977ATG - II - ...
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... Set5.Reg0 Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL) ...............69 7.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) ...........................................................69 7.7.3 Set5.Reg3 - Sets Select Register (SSR) ..............................................................................70 7.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)...........................................................70 7.7.5 Set5.Reg5 - Frame Status FIFO Register (FS_FO) .............................................................71 W83977ATF/W83977ATG Publication Release Date: May 2006 - III - Revision 0.6 ...
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... FIFO Mode) Mode = 110 .....................................................................................92 8.3.8 cnfgA (Configuration Register A) Mode = 111 ......................................................................92 8.3.9 cnfgB (Configuration Register B) Mode = 111 ......................................................................92 8.3.10 ecr (Extended Control Register) Mode = all..........................................................................93 8.3.11 Bit Map of ECP Port Registers .............................................................................................94 8.3.12 ECP Pin Descriptions ...........................................................................................................95 8.3.13 ECP Operation .....................................................................................................................96 8.3.14 FIFO Operation ....................................................................................................................96 8.3.15 DMA Transfers .....................................................................................................................97 W83977ATF/W83977ATG - IV - ...
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... Power Management 1 Control Register 3 (PM1CTL3) .......................................................119 12.3.8 Power Management 1 Control Register 4 (PM1CTL4) .......................................................119 12.3.9 Power Management 1 Timer 1 (PM1TMR1) .......................................................................120 12.3.10 Power Management 1 Timer 2 (PM1TMR2) .......................................................................120 12.3.11 Power Management 1 Timer 3 (PM1TMR3) .......................................................................121 12.3.12 Power Management 1 Timer 4 (PM1TMR4) .......................................................................121 W83977ATF/W83977ATG Publication Release Date: May 2006 - V - Revision 0.6 ...
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... EPP Data or Address Write Cycle Timing Parameters .......................................................169 15.3.6 Parallel Port FIFO Timing Parameters................................................................................170 15.3.7 ECP Parallel Port Forward Timing Parameters ..................................................................170 15.3.8 ECP Parallel Port Reverse Timing Parameters ..................................................................170 15.3.9 KBC Timing Parameters.....................................................................................................171 15.3.10 GPIO Timing Parameters ...................................................................................................172 16. TIMING WAVEFORMS................................................................................................................ 173 W83977ATF/W83977ATG - VI - ...
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... APPLICATION CIRCUITS ........................................................................................................... 185 17.1 Parallel Port Extension FDD.............................................................................................. 185 17.2 Parallel Port Extension 2FDD............................................................................................ 186 17.3 Four FDD Mode................................................................................................................. 186 18. ORDERING INFORMATION ....................................................................................................... 187 19. HOW TO READ THE TOP MARKING ........................................................................................ 188 20. PACKAGE DIMENSIONS............................................................................................................ 189 W83977ATF/W83977ATG Publication Release Date: May 2006 - VII - Revision 0.6 ...
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... W83977ATF/ATG is made to meet the specification of PC97's requirement in the power management: ACPI and DPM (Device Power Management). Another benefit is that W83977ATF/ATG has the same pin assignment as W83977AF, W83977F, and W83977TF. This makes the design very flexible. W83977ATF/W83977ATG Publication Release Date: May 2006 - ...
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... Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation • Programmable baud generator allows division of 1.8461 Mhz and 24 Mhz • Maximum baud rate up to 921k bps for 14.769 Mhz and 1.5M bps for 24 Mhz W83977ATF/W83977ATG - -1) ...
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... I/O ports; 1 dedicate, 22 optional • General purpose I/O ports can serve as simple I/O ports, interrupt steering inputs, watching dog timer output, power LED output, infrared I/O pins, general purpose address decoder, KBC control I/O pins W83977ATF/W83977ATG TM TM -2, Phoenix MultiKey/42 ...
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... OnNow Funtions • Keyboard wake-up by programmable keys (patent pending) • Mouse wake-up by programmable buttons (patent pending) • CIR wake-up by programmable keys (patent pending) Package • 128-pin PQFP W83977ATF/W83977ATG - 4 - ...
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... IOR 106 IOW AEN 107 IOCHRDY 108 109 D0 D1 110 111 D2 112 D3 113 D4 D5 114 115 VCC 116 D6 117 D7 118 MR 119 DACK0/GP16 120 VSS 121 SCI/DRQ0/GP17 122 DACK1 123 DRQ1 124 DACK2 DRQ2 125 126 DACK3 127 DRQ3 TC 128 W83977ATF/W83977ATG ...
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... IN ts IOCHRDY 108 OD24 MR 118 INts W83977ATF/W83977ATG FUNCTION System address bus bits 0-10. System address bus bits 11-14. System address bus bit 15. System data bus bits 0-5. System data bus bits 6-7. CPU I/O read signal. CPU I/O write signal. ...
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... I/O12t IRQ6 95 OUT12t GP34 I/O12t W83977ATF/W83977ATG FUNCTION DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00, default) General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01) Alternate function from GP16: Watch dog timer output. KBC P15 I/O port. (CR2C bit 5_4 = 10) DMA Channel 0 request signal. (CR2C bit 7_6 = 00, default) General purpose I/O port 1bit 7 ...
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... WDT OUT 12t CLKIN W83977ATF/W83977ATG FUNCTION Interrupt request 7. (Logical device 9, CRF1 bit General purpose I/O port 3 bit 5. (Logical device 9, CRF1 bit Interrupt request 8. (Logical device 9, CRF1 bit General purpose I/O port 3 bit 6. (Logical device 9, CRF1 bit Interrupt request 9. (Logical device 9, CRF1 bit General purpose I/O port 3 bit 7 ...
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... IRRXH IN t IRSL0 OUT 12t W83977ATF/W83977ATG FUNCTION General purpose I/O port 2 bit 0. Alternate Function from GP20: Keyboard reset. (KBC P20) System Management Interrupt. (CR2B bit 4_3 = 00, default) In the legacy power management mode, managenment events. General purpose I/O port 2 bit 1. (CR2B bit 4_3 = 01) Alternate Function from GP21: KBC P13 I/O port ...
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... IN RIA t 66 RIB W83977ATF/W83977ATG FUNCTION Clear To Send. This is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. ...
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... OD 12 BUSY 21 INt OD12 OD12 W83977ATF/W83977ATG FUNCTION Infrared Receiver input. Infrared Transmitter Output. FUNCTION PRINTER MODE: SLCT An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. ...
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... OD12 SLIN OD12 OD12 W83977ATF/W83977ATG FUNCTION ACK PRINTER MODE: An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode ...
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... STB PD0 31 I/O24t INt INt W83977ATF/W83977ATG FUNCTION INIT PRINTER MODE: Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. DIR2 EXTENSION FDD MODE: This pin is for Extension FDD B; its function is the same as the of FDC ...
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... IN t PD4 27 I/O24t INt INt W83977ATF/W83977ATG FUNCTION PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. TRAK02 EXTENSION FDD MODE: This pin is for Extension FDD B; its function is the same as the pin of FDC ...
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... W83977ATF/W83977ATG FUNCTION PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: This pin is a tri-state output. ...
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... IN TRAK0 INDEX cs W83977ATF/W83977ATG FUNCTION Step output pulses. This active low open drain output produces a pulse to move the head to another track. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Motor B On. When set to 0, this pin enables disk drive 1. This is an open drain output ...
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... NA XTAL1 XTAL2 W83977ATF/W83977ATG FUNCTION Keyboard Data. PS2 Mouse Data. Keyboard Clock. PS2 Mouse Clock. KBC GATE A20 (P21) Output. (CR2A bit default) General purpose I/O port 1 bit 1. (CR2A bit Alternate Function from GP11: Interrupt channel input. W83C45 Keyboard Reset (P20) Output. (CR2A bit default) General purpose I/O port 1 bit 2 ...
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... Byte 15 Byte FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte W83977ATF/W83977ATG MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 1 × 16 μS - 1.5 μS = 14.5 μS 2 × 16 μS - 1.5 μS = 30.5 μS 8 × 16 μS - 1.5 μS = 6.5 μS 15 × 16 μS - 1.5 μS = 238.5 μS MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 1 × ...
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... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. W83977ATF/W83977ATG Publication Release Date: May 2006 - 19 - ...
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... Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten W83977ATF/W83977ATG - 20 - ...
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... H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977ATF/W83977ATG HDS DS1 DS0 - REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after ...
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... Command W 0 MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977ATF/W83977ATG HDS DS1 DS0 HDS DS1 DS0 - REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system ...
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... Verify PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977ATF/W83977ATG HDS DS1 DS0 HDS DS1 DS0 - REMARKS 0 Command codes The first correct ID information on the cylinder is stored in Data Register ...
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... D7 Command W 0 Result R 1 (7) Write Data PHASE R/W D7 Command W MT MFM ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977ATF/W83977ATG HDS DS1 DS0 - REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes Sector ID information prior ...
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... H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83977ATF/W83977ATG HDS DS1 DS0 - REMARKS 1 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after ...
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... Each W ---------------------- H ------------------------ Sector W ---------------------- R ------------------------ Repeat: W ---------------------- N ------------------------ Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command Execution (11) Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- W83977ATF/W83977ATG HDS DS1 DS0 DS1 DS0 REMARKS 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte ...
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... Specify PHASE R/W D7 Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND (13) Seek PHASE R/W D7 Command -------------------- NCN ----------------------- Execution R (14) Configure PHASE R/W D7 Command EIS EFIFO POLL | ------ FIFOTHR ----| W | --------------------PRETRK ----------------------- | Execution (15) Relative Seek PHASE R/W D7 Command W 1 DIR -------------------- RCN ---------------------------- | W83977ATF/W83977ATG HDS DS1 DS0 HDS DS1 DS0 ...
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... HLT -----------------------------------| ND R ------------------------ SC/EOT ---------------------- R LOCK EIS EFIFO POLL | ------ FIFOTHR -------- R -----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R/W D7 Command (18) Lock PHASE R/W D7 Command W LOCK 0 Result R 0 (19) Sense Drive Status PHASE R/W D7 Command Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R/W D7 Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- W83977ATF/W83977ATG GAP GAP LOCK ...
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... DRV2 (Bit 6 second drive has been installed 1 A second drive has not been installed STEP (Bit 5): This bit indicates the complement of STEP output. TRAK0 (Bit 4): This bit indicates the value of TRAK0 input. W83977ATF/W83977ATG READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER DI REGISTER 2 ...
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... This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. W83977ATF/W83977ATG ...
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... This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin. WE (Bit 2): This bit indicates the complement of the WE output pin. W83977ATF/W83977ATG ...
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... This bit indicates the complement of the latched RDATA output pin. WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected W83977ATF/W83977ATG DSC DSD WE F/F RDATA F/F ...
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... This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows: If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows: 7 W83977ATF/W83977ATG 3 1-0 2 Drive Select: 00 select drive A ...
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... The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER. W83977ATF/W83977ATG TAPE SEL ...
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... DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S W83977ATF/W83977ATG DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) DEFAULT PRECOMPENSATION DELAYS 125 nS 125 nS 41.67nS 20.8 nS ...
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... In W83977ATF/ATG, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. Status Register 0 (ST0) 7 1-0 4 W83977ATF/W83977ATG US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected HD Head address: 1 Head selected 0 Head selected ...
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... Status Register 3 (ST3 W83977ATF/W83977ATG 0 Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA specified sector cannot be found during execution of a read, write or verifly data. ...
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... DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates. HIGH DENS (Bit 0): 0 500 KB MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate W83977ATF/W83977ATG ...
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... These two bits select the data rate of the FDC. 5.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows Reserved Bit 7-2: Reserved. These bits should be set to 0. W83977ATF/W83977ATG ...
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... In the PS/2 Model 30 mode, the bit definitions are as follows Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. W83977ATF/W83977ATG ...
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... Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check. (2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check. W83977ATF/W83977ATG ...
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... BDLAB Low + 1 Baudrate BHL Bit 8 Divisor Latch = 1 BDLAB High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. W83977ATF/W83977ATG BIT NUMBER Data RX Data RX Data Bit 1 Bit 2 Bit 3 ...
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... Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO. W83977ATF/W83977ATG DLS0 0 1 ...
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... RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0. 6.2.3 Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART W83977ATF/W83977ATG Data terminal ready (DTR) ...
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... Bit 5: This bit is the opposite of the DSR input. This bit is equivalent to bit 0 of HCR in loopback mode. Bit 4: This bit is the opposite of the CTS input. This bit is equivalent to bit 1 of HCR in loopback mode. Bit 3: TDCD. This bit indicates that the DCD pin has changed state after HSR was read by the CPU. W83977ATF/W83977ATG ...
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... Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed. W83977ATF/W83977ATG ...
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... First Second Second Third Fourth ** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1. W83977ATF/W83977ATG INTERRUPT SET AND FUNCTION Interrupt Type Interrupt Source - - No Interrupt pending UART Receive 1. OER = 1 Status 3. NSER = 1 4. SBD = 1 RBR Data 1. RBR data ready Ready 2. FIFO interrupt active level ...
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... The table in the next page illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps. W83977ATF/W83977ATG ...
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... The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Note. Pre-Divisor is determined by CRF0 of UART A and B. W83977ATF/W83977ATG Pre-Div: 1.0 Decimal divisor used to generate 16X clock 24M Hz 650 2304 975 1536 1430 1047 1478 ...
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... UART Registers *Set 2~7 are Advanced UART Registers Each of these register sets has a common register, namely Sets Select Register (SSR), in order to switch to another register set. The summary description of these Sets is given below. W83977ATF/W83977ATG Set 1 Set 2 Set 3 Set 4 ...
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... TX/RX DMA channel is swapped. Note that two DMA channels can be defined in configure register CR2A, which selects DMA channel or disables DMA channel. If only RX DMA channel is enabled while TX DMA channel is disabled, then the single DMA channel will be selected. W83977ATF/W83977ATG SETS DESCRIPTION Receiver/Transmitter Buffer Registers ...
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... ETXTHI - Enable Transmitter Threshold Interrupt A write to 1 will enable transmitter threshold interrupt. Bit 4: Legacy IR Mode: Not used. A read will return 0. MIR, FIR, Remote IR: EDMAI - Enable DMA Interrupt. A write to 1 will enable DMA interrupt. Bit 3: Reserved. A read will return 0. W83977ATF/W83977ATG ETXTHI EDMAI 0 ...
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... Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred, this bit will be set to logical 0. W83977ATF/W83977ATG ...
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... Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASK- IR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake Status Enable (IRHS_EN) is set to 1. W83977ATF/W83977ATG INTERRUPT SET AND FUNCTION Interrupt Interrupt Source ...
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... Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active level is set as 4 bytes and there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify CPU to read the data from FIFO. W83977ATF/W83977ATG BIT 5 BIT 4 ...
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... Note that the FIFO Size is selectable in SET2.Reg4. Bit 5, 4: TXFTL1 Transmitter FIFO Threshold Level TXTH_I (Transmitter Threshold Level Interrupt) is set to 1 when the Transmitter Threshold Level is less than the programmed value shown below. W83977ATF/W83977ATG RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) RX FIFO THRESHOLD LEVEL (FIFO SIZE: 16-BYTE) 1 ...
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... Any combination except those used in SET 2 7.2.5 Set0.Reg4 - Handshake Control Register (HCR) MODE B7 B6 Legacy Advanced IR AD_MD2 AD_MD1 AD_MD0 SIR_PLS Reset Value 0 1 W83977ATF/W83977ATG TX FIFO THRESHOLD LEVEL (FIFO SIZE: 16-BYTE SSR BITS ¡Ñ ¡Ñ ¡Ñ ¡Ñ ...
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... If this bit is set to 1, the transmitter will wait for TX FIFO to reach threshold level or transmitter time-out before it begins to transmit data; this prevents short queues of data bytes from transmitting prematurely. This is to avoid Underrun. Other Modes: Not used. W83977ATF/W83977ATG SELECTED MODE Reserved Low speed MIR (0.576M bps) ...
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... Bit 2: MIR, FIR Modes: CRC_ERR - CRC Error Set to 1 when an attached CRC is erroneous. Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready Definitions are the same as legacy IR. W83977ATF/W83977ATG B5 B4 TBRE SBD TBRE MX_LEX PHY_ERR CRC_ERR ...
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... An Entire Frame = Write Frame Data (First) + Write S_FEND (Last) This bit should be set used in PIO mode, to avoid transmitter underrun. Note that setting S_FEND equivalent to TC (Terminal Count) in DMA mode. Therefore, this bit should be set DMA mode. Bit 2: Reserved. W83977ATF/W83977ATG BIT 5 BIT 4 BIT 3 Bit 5 Bit 4 ...
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... Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is meaningful in legacy SIR/ASK-IR. 7.3.2 Set1.Reg 2~7 These registers are defined the same as Set 0 registers. W83977ATF/W83977ATG Baud Rate Divisor Latch (Low Byte) BLL Baud Rate Divisor Latch (High Byte) BHL ...
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... EN_LOUT - Enable Loopback Output A write to 1 will enable transmitter to output data to IRTX pin when loopback operation occurs. Internal data can be verified through an output pin by setting this bit. W83977ATF/W83977ATG ABLL Advanced Baud Rate Divisor Latch (Low Byte) Advanced Baud Rate Divisor Latch (High Byte) ...
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... Reg3 - Sets Select Register (SSR) Reading this register returns E0H. Writing a value selects Register Set. REG. BIT 7 BIT 6 SSR SSR7 SSR6 Refault Value 1 W83977ATF/W83977ATG DMA Channel Selected 0 Receiver (Default) 1 Transmitter TX FIFO THRESHOLD 16-BYTE 13 23 Function Description DMA request (DREQ) is forced inactive after 10.5us No effect DMA request ...
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... RX_FSZ1~0 - Receiver FIFO Size 1~0 These bits setup receiver FIFO size when FIFO is enable. RX_FSZ1 Bit 1, 0: TX_FSZ1~0 - Transmitter FIFO Size 1~0 These bits setup transmitter FIFO size when FIFO is enable. TX_FSZ1 W83977ATF/W83977ATG BIT 5 BIT 4 BIT 3 - PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 PRE-DIVISOR 13.0 1.625 6 ...
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... Advanced IR 0 Reset Value 0 Bit 7~6: Reserved, Read 0. Bit 5~0: Reading these bits returns the current transmitter FIFO depth, that is, the number of bytes left in the transmitter FIFO. W83977ATF/W83977ATG Pre-Div: 1.0 Decimal divisor used to generate 16X clock 24M Hz 650 2304 975 1536 ...
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... Reg1 - Mapped IR Control Register (MP_UCR) This register is read only. Reading this register returns IR Control Register value of Set 0. REG. BIT 7 BIT 6 SSR SSR7 SSR6 Default Value 0 0 W83977ATF/W83977ATG BIT 5 BIT 4 0 RXFD5 RXFD4 RXFD3 Mapped IR FIFO Control Register SSR BIT 5 BIT 4 ...
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... When the timer counts down to zero and EN_TMR=1, the TMR_I is set to 1 and a new initial value will be loaded into counter. 7.6.2 Set4.Reg2 - Infrared Mode Select (IR_MSL) MODE BIT 7 BIT 6 Advanced Reset Value 0 0 W83977ATF/W83977ATG BIT 5 BIT 4 BIT 3 SSR5 SSR4 SSR3 0 0 BIT 5 BIT 4 BIT 3 SSR5 ...
Page 76
... Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame length if the transmitted data is larger than the programmed frame length. When these registers are read, they will return the number of bytes which is not transmitted from a frame length programmed. W83977ATF/W83977ATG OPERATION MODE SELECTED BIT 5 ...
Page 77
... FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL). 7.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD) These registers control flow control mode operation as shown in the following table. REG. BIT 7 BIT 6 FC_MD FC_MD2 FC_MD1 Reset 0 0 Value W83977ATF/W83977ATG BIT 6 BIT 5 BIT 4 bit 6 bit 5 bit bit 12 - ...
Page 78
... FSF_TH - Frame Status FIFO Threshold Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I. The threshold level values are defined as follows. FSF_TH 0 1 W83977ATF/W83977ATG Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel BIT 5 BIT 4 ...
Page 79
... IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready). Bit 1: RX_OV - Received Data Overrun Set to 1 when receiver FIFO overruns. Bit 0: FSF_OV - Frame Status FIFO Overrun Set to 1 When frame status FIFO overruns. W83977ATF/W83977ATG BIT 5 BIT 4 BIT 3 - MX_LEX PHY_ERR CRC_ERR 0 ...
Page 80
... Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2) This register controls ASK-IR, MIR, FIR operations. REG. BIT 7 BIT 6 IR_CFG2 SHMD_N SHDM_N Reset Value 0 Bit 7: SHMD_N - ASK-IR Modulation Disable SHMD_N W83977ATF/W83977ATG BIT 6 BIT 5 BIT 4 Bit 6 Bit 5 Bit Bit IR_CFG2 Infrared Configure Register 2 MIR_PW MIR (1.152M bps or 0.576M bps) Pulse Width ...
Page 81
... Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width REG. BIT 7 BIT 6 MIR_PW - Reset Value 0 This 5-bit register sets MIR output pulse width. M_PW4~0 MIR PULSE WIDTH (1.152M BPS) 00000 00001 00010 ... k 10 ... 11111 W83977ATF/W83977ATG Demodulation Mode 0 Demodulation 500K BIT 5 BIT 4 BIT M_PW4 M_PW3 ...
Page 82
... MIR start flag should be equal or more than two which is defined in IrDA 1.1 physical layer. The default value is 2. M_FG3~0 BEGINNING FLAG NUMBER 0000 0001 0010 0011 0100 0101 0110 0111 W83977ATF/W83977ATG BIT 5 BIT S_PW4 S_PW3 SIR OUTPUT PULSE WIDTH 3/16 bit time of IR ...
Page 83
... IRM_SL1 5 IRM_SL2 6 IRM_SL3 7 IRM_CR 7.9.1 4.9.1 Set7.Reg0 - Remote Infrared Receiver Control (RIR_RXC) REG. BIT 7 BIT 6 RIR_RXC RX_FR2 RX_FR1 Default Value 0 This register defines frequency range of receiver of remote IR. W83977ATF/W83977ATG M_FG3~0 1000 1 1001 2 1010 3 1011 4 1100 5 1101 6 1110 8 1111 REGISTER DESCRIPTION Remote Infrared Receiver Control ...
Page 84
... Note that those unassigned combinations are reserved. W83977ATF/W83977ATG RX_FR2~0 (LOW FREQUENCY) 010 Max. Min. Max. 29.6 24.7 31.7 32.0 26.7 34.3 33.3 27.8 35.7 34.0 28.4 36 ...
Page 85
... Select the transmission pulse width. TX_PW2~0 010 011 100 101 Note that those unassigned combinations are reserved. Bit 4~0: TX_FSL4~0 - Transmitter Frequency Select 4~0. Select the transmission frequency. W83977ATF/W83977ATG RX_FR2~0 (HIGH FREQUENCY) Min. 355.6 380.1 410.3 RX_FSL4~0 (SHARP ASK-IR) 010 011 100 436 ...
Page 86
... Set7.Reg2 - Remote Infrared Config Register (RIR_CFG) REG. BIT 7 BIT 6 RIR_CFG P_PNB SMP_M Default Value 0 0 Bit 7: P_PNB: Programming Pulse Number Coding. Write select programming pulse number coding. The code format is defined as follows. W83977ATF/W83977ATG BIT 5 BIT 4 BIT 3 RXCFS - TX_CFS 0 0 (Number of bits Bit value ...
Page 87
... REG. BIT 7 BIT 6 SSR Bit 7 Bit 6 Default Value 1 Reading this register returns F4H. Select Register Set by writing a set number to this register. W83977ATF/W83977ATG Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Demodulation Mode Enable internal decoder Disable internal decoder ...
Page 88
... AD_MD2~0 are configured to FIR mode. These values will be automatically loaded to IR_SL2~0, respectively. Bit 3: Reserved, write 0. Bit 2~0: MIR_SL2~0 - MIR Mode Select. These bits setup the MIR operational mode when AM_FMT=1 and AD_MD2~0 are configured to MIR mode. respectively. W83977ATF/W83977ATG BIT 5 BIT 4 SIR_SL1 SIR_SL0 BIT 5 ...
Page 89
... If the IR module has only one receiving path, then this bit should be set to 0. IRX_MSL 0 1 Bit 5: IRSL0D - Direction of IRSL0 Pin Select function for IRRXH or IRSL0 because they share common pin and have different input/output direction. IRSL0_D 0 1 W83977ATF/W83977ATG BIT 5 BIT 4 LRC_SL1 LRC_SL0 BIT 5 BIT 4 IRSL0D RXINV ...
Page 90
... IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver. Bit 4: RXINV - Receiving Signal Invert A write to 1 will Invert the receiving signal. Bit 3: TXINV - Transmitting Signal Invert A write to 1 will Invert the transmitting signal. Bit 2~0: Reserved, write 0. W83977ATF/W83977ATG AUX_RX HIGH SPEED ...
Page 91
... PIN NUMBER CONNECTOR OF W83977ATF 1 36 2-9 31-26, 24- Notes: n<name > : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, refer to the IEEE 1284 standard. W83977ATF/W83977ATG PIN SPP ATTRIBUTE O nSTB nWrite I/O PD<0:7> PD<0:7> I nACK I BUSY SLCT O nAFD nDStrb I nERR O nINIT O nSLIN nAStrb - 83 - ...
Page 92
... Enhanced Parallel Port (EPP) TABLE 8-2 PRINTER MODE AND EPP REGISTER ADDRESS Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. W83977ATF/W83977ATG PIN PIN SPP ATTRIBUTE ATTRIBUTE O nSTB --- I/O PD0 I I/O PD1 I I/O PD2 I I/O PD3 I I/O PD4 I I/O ...
Page 93
... Bit 0: This bit is valid in EPP mode only. It indicates that a 10 μS time-out has occurred on the EPP bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect. W83977ATF/W83977ATG ...
Page 94
... The leading edge of IOW trailing edge of IOW latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read during a read operation. The leading edge of IOR causes an EPP address read cycle to be performed and the data to be output to the host CPU. W83977ATF/W83977ATG ...
Page 95
... Status Buffer (Read) BUSY Control Swapper 1 (Read) Control Latch (Write) 1 EPP Address Port PD7 R/W) EPP Data Port 0 PD7 (R/W) EPP Data Port 1 PD7 (R/W) EPP Data Port 2 PD7 (R/W) EPP Data Port 3 PD7 (R/W) W83977ATF/W83977ATG PD6 PD5 PD4 PD3 PE SLCT ACK ERROR 1 ...
Page 96
... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. W83977ATF/W83977ATG EPP DESCRIPTION - 88 - ...
Page 97
... EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode Note: The mode selection bits are bit 7-5 of the Extended Control Register. W83977ATF/W83977ATG I/O ECP MODES R/W 000-001 Data Register R/W 011 ECP FIFO (Address) ...
Page 98
... ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows 8.3.3 Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows: W83977ATF/W83977ATG ...
Page 99
... Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned. W83977ATF/W83977ATG ...
Page 100
... Register B) Mode = 111 The bit definitions are as follows: 7 Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. W83977ATF/W83977ATG ...
Page 101
... Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected. 101 Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. W83977ATF/W83977ATG IRQ resource ...
Page 102
... Parallel Port Data FIFO ecpDFifo ECP Data FIFO tFifo Test FIFO cnfgA 0 0 cnfgB compress intrValue ecr MODE Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. W83977ATF/W83977ATG PD5 PD4 PD3 PError Select nFault SelectIn Directio ackIntEn ...
Page 103
... PError (nAckReverse) Select (Xflag) nAutoFd (HostAck) nFault (nPeriphRequest) nInit (nReverseRequest) nSelectIn (ECPMode) W83977ATF/W83977ATG O The nStrobe registers data or address into the slave on the asserting edge during write operations. This signal handshakes with Busy. These signals contain address or data or RLE data. I This signal indicates valid data driven by the peripheral when asserted. ...
Page 104
... The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. W83977ATF/W83977ATG - 96 - ...
Page 105
... Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. W83977ATF/W83977ATG Publication Release Date: May 2006 - 97 - Revision 0.6 ...
Page 106
... Data written to I/O address 60H is sent to keyboard (unless the keyboard controller is expecting a data byte) through the controller's input buffer only if the input buffer full bit in the status register is “0”. W83977ATF/W83977ATG P24 P25 ...
Page 107
... Commands COMMAND 20h Read Command Byte of Keyboard Controller 60h Write Command Byte of Keyboard Controller W83977ATF/W83977ATG 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set writing to the system flag bit in the command byte of the keyboard controller. It defaults to 0 after a power-on reset ...
Page 108
... Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts the upper four bits of Port1 into STATUS register D0h Send Port2 value to the system D1h Only set/reset GateA20 line based on the system data bit 1 W83977ATF/W83977ATG FUNCTION BIT BIT DEFINITION 00 No Error Detected 01 Auxiliary Device " ...
Page 109
... When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATE A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse low for 6 μ S (Min.) with 14 μ S (Min.) delay. W83977ATF/W83977ATG FUNCTION 5 4 ...
Page 110
... A "1" on this bit drives GATE A20 signal to high. A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6 μ S (Min.) with 14 μ S (Min.) delay. Before issuing another keyboard reset command, the bit must be cleared. W83977ATF/W83977ATG Res. (1) Res ...
Page 111
... I/O ports functions by independently programming the configuration registers. Figure 7.1, 7.2, and 7.3 show the GP I/O port's structure of logical device 7, 8, and 9 respectively. Right after Power-on reset, those ports default to perform basic I/O functions. W83977ATF/W83977ATG Figure 10.1 Publication Release Date: May 2006 - 103 - Revision 0 ...
Page 112
... W83977ATF/W83977ATG Figure 10.2 Figure 10.3 - 104 - ...
Page 113
... OUTPUT 0 = DISABLE 1 = INPUT 1 = ENABLE W83977ATF/W83977ATG POLARITY BIT BASIC I/O OPERATIONS 0 = NON INVERT 1 = INVERT 0 Basic non-inverting output 1 Basic inverting output 0 Non-inverted output bit value of GP2 drive to Common Interrupt 1 Inverted output bit value of GP2 drive to Common Interrupt 0 Basic non-inverting input 1 Basic inverting input 0 ...
Page 114
... Table 10.1.2 GP I/O PORT ACCESSED REGISTER GP1 GP2 GP3 W83977ATF/W83977ATG REGISTER BIT ASSIGNMENT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 - 106 - GP I/O PORT GP10 GP11 ...
Page 115
... IRQ channel can be done in configuration registers CR70 and CR72 of logical device 7 and logical device 9. Each interrupt channel also has its own 1 ms debounce filter that is used to reject any noise whose width is equal to or less than 1 ms. W83977ATF/W83977ATG ALTERNATE FUNCTION Publication Release Date: May 2006 - 107 - Revision 0 ...
Page 116
... General Purpose Write Strobe is an address decoder that performs like General Purpose Address Decoder, but it has to be qualified by IOW and AEN. Its output is normally active low. Users can alter its polarity through the polarity bit of the GP15's configuration register. W83977ATF/W83977ATG WDT_CTRL1 BIT[0] X ...
Page 117
... The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. W83977ATF/W83977ATG ADDRESS AND VALUE Publication Release Date: May 2006 - 109 - ...
Page 118
... EFDR. Exit the extended function mode To exit the extended function mode, one write of 0xAA to EFER is required. Once the chip exits the extended function mode the normal running mode and is ready to enter the configuration mode. W83977ATF/W83977ATG W83977ATF/ATG enters the - 110 - ...
Page 119
... AL, 01H OUT DX select logical device 1 ; MOV DX, 3F0H MOV AL, F0H OUT DX select CRF0 MOV DX, 3F1H MOV AL, 3CH OUT DX update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOV DX, 3F0H MOV AL, AAH OUT DX, AL W83977ATF/W83977ATG | - 111 - | Publication Release Date: May 2006 Revision 0.6 ...
Page 120
... The SCI interrupt can be routed to pin SCI , which is dedicated for the SCI function can be routed to one interrupt request pin, which is selected through CR70 bit3-0 of logical device A. Another way is to output the SCI interrupt to pin IRQSER if Serial IRQ mode is enabled. W83977ATF/W83977ATG SMI_EN SMI Logic ...
Page 121
... BIOS_EN is the enable bit and the BIOS_STS is the status bit. Both are controlled by the BIOS software. If GBL_RLS is set by the ACPI software and BIOS_EN is set by the BIOS software, a SMI is raised. Writing GBL_RLS sets it to logic 1 and also sets BIOS_STS to logic W83977ATF/W83977ATG clear GBL_STS ...
Page 122
... The TMR_ON is located in GPE register block cleared to 0, the power management timer function will not work. There are no timer reset requirements, except that the timer should function after power-up. See the following figure for illustration. TMR_ON 3.579545 MHz W83977ATF/W83977ATG TMR_STS 24 bit counter Bits (23-0) ...
Page 123
... A. The base address of general-purpose event block GPE1 is named as GPE1_BLK in the ACPI specification and is specified in CR64, CR65 of logical device A. 12.3.1 Power Management 1 Status Register 1 (PM1STS1) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 W83977ATF/W83977ATG 115 - 0 TMR_STS Reserved Reserved ...
Page 124
... Writing a 0 has no effect. When the WAK_STS is cleared and all devices are in sleeping state, the whole chip enters the sleeping state. W83977ATF/W83977ATG DESCRIPTION 2 1 ...
Page 125
... SCI interrupt is raised. 6-7 Reserved Reserved. 12.3.4 Power Management 1 Enable Register 2 (PM1EN2) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 BIT NAME 0-7 Reserved Reserved. These bits always return zeros. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION - 117 - 0 TMR_EN Reserved ...
Page 126
... Reserved Reserved. These bits always return zeros. 12.3.6 Power Management 1 Control Register 2 (PM1CTL2) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 BIT NAME 0-7 Reserved Reserved. These bits always return zeros. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION - 118 - ...
Page 127
... Reserved Reserved. These bits always return zeros. 12.3.8 Power Management 1 Control Register 4 (PM1CTL4) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 BIT NAME 0-7 Reserved Reserved. These bits always return zeros. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION - 119 - 0 ...
Page 128
... If the clock is restarted without an MR reset, then the counter will resume counting from where it stopped. The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an W83977ATF/W83977ATG ...
Page 129
... If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an 12.3.12 Power Management 1 Timer 4 (PM1TMR4) Register Location: <CR60, 61> System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits 7 BIT NAME 0-7 Reserved Reserved. These bits always return zeros. W83977ATF/W83977ATG DESCRIPTION SCI interrupt DESCRIPTION ...
Page 130
... Reserved Reserved. 12.3.14 General Purpose Event 0 Status Register 2 (GP0STS2) Register Location: <CR62, 63> System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits W83977ATF/W83977ATG DESCRIPTION SCI status, which is set by the UART B IRQ. SCI status, which is set by the UART A IRQ. status, which is set by the FDC IRQ. ...
Page 131
... PRTSCIEN Printer port SCI enable, which controls the printer port IRQ. 4 KBCSCIEN KBC SCI enable, which controls the KBC IRQ. 5 MOUSCIEN MOUSE SCI enable, which controls the MOUSE IRQ. 6 IRSCIEN IR SCI enable, which controls the IR IRQ. 7 Reserved Reserved. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION ...
Page 132
... Attribute: Read/write Size: 8 bits 7 BIT NAME 0 BIOS_STS The BIOS status bit. This bit is set when GBL_RLS is set. If BIOS_EN is set, setting GBL_RLS will raise an and also clears GBL_RLS. Writing a 0 has no effect. 1-7 Reserved Reserved. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION SMI event. Writing its bit location clears BIOS_STS ...
Page 133
... Size: 8 bits 7 BIT NAME 0 BIOS_EN This bit raises the to the GBL_RLS bit TMR_ON This bit is used to turn on the power management timer timer on timer off. 2-7 Reserved Reserved. W83977ATF/W83977ATG DESCRIPTION DESCRIPTION SMI event. When this bit is set and the ACPI software writes a 1 ...
Page 134
... This bit is used to set the BM_STS bit and if the BM_RLD bit is also set, then an SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets BM_STS. Writing a 0 has no effect. Writing BM_STS clears BM_STS and also clears BM_CNTRL. 2-7 Reserved Reserved. W83977ATF/W83977ATG ...
Page 135
... GP0STS2 <CR62, 0000 0000 63>+1H GP0EN1 <CR62, 0000 0000 63>+2H GP0EN2 <CR62, 0000 0000 63>+3H GP1STS1 <CR64, 0000 0000 65> GP1STS2 <CR64, 0000 0000 65>+1H GP1EN1 <CR64, 0000 0000 65>+2H GP1EN2 <CR64, 0000 0000 65>+3H W83977ATF/W83977ATG GBL_STS BM_STS GBL_EN ...
Page 136
... Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2. There may be none, one or more Idle states during the Stop Frame. 3. The next IRQSER cycle's Start Frame pulse may or may not start immediately after the turn-around clock of the Stip Frame. W83977ATF/W83977ATG IRQ0 FRAME R ...
Page 137
... The IRQ/Data Frame has a number of specific order, as shown in Table 13-1. Table 13-1 IRQSER Sampling periods IRQ/DATA FRAME W83977ATF/W83977ATG SIGNAL SAMPLED # OF CLOCKS PAST START IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 Publication Release Date: May 2006 ...
Page 138
... IRQSER cycle is performed. For IRQSER system suspend, insertion, or removal application, the Host controller should be programmed into Continuous (Idle) mode first. This is to guarantee IRQSER bus in the Idle state before the system configuration changes. W83977ATF/W83977ATG SIGNAL SAMPLED # OF CLOCKS PAST START IRQ13 ...
Page 139
... No Power down Bit 1 : Reserved. Bit 0 : FDCPWD = 0 Power down = 1 No Power down CR23 (Default 0xFE) Bit Reserved. Bit 0 : IPD (Immediate Power Down). When set will put the whole chip into power down mode immediately. W83977ATF/W83977ATG Publication Release Date: May 2006 - 131 - Revision 0.6 ...
Page 140
... PNPCSV is 1. The corresponding power-on setting pin is NDTRA (pin 44). CR25 (Default 0x00) Bit Reserved Bit 5 : URBTRI Bit 4 : URATRI Bit 3 : PRTTRI Bit 2 : IRTRI Bit 1 : Reserved Bit 0 : FDCTRI. CR26 (Default 0b0s000000) Bit 7 : SEL4FDD = 0 Select two FDD mode Select four FDD mode. W83977ATF/W83977ATG - 132 - ...
Page 141
... Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ CR28 (Default 0x00) Bit Reserved. Bit 4 : IRQ Sharing selection Disable IRQ Sharing = 1 Enable IRQ Sharing Bit 3 :Reserved W83977ATF/W83977ATG on selecting IRQ - 133 - Publication Release Date: May 2006 Revision 0.6 ...
Page 142
... GP12 Bit 6 : PIN56S = 0 GA20 = 1 GP11 Bit PIN40S1, PIN40S0 = 00 CIRRX = 01 GP24 = 10 8042 P13 = 11 Reserved Bit PIN39S1, PIN39S0 = 00 IRRXH = 01 IRSL0 = 10 GP25 =11 Reserved Bit PIN3S1, PIN3S0 = 00 DRVDEN1 = 01 GP10 = 10 8042 P12 = 11 SCI CR2B (Default 0x00) Bit PIN73S1, PIN73S0 = 00 PANSWIN = 01 GP23 = 10 Reserved = 11 Reserved W83977ATF/W83977ATG - 134 - ...
Page 143
... SCI Bit PIN119S1, PIN119S0 = 00 NDACK0 = 01 GP16 = 10 8042 P15 = 11 Reserved Bit PIN104S1, PIN104S0 = 00 IRQ15 = 01 GP15 = 10 WDTO = 11 Reserved Bit PIN103S1, PIN103S0 = 00 IRQ14 = 01 GP14 = 10 PLEDO = 11 Reserved CR2D (Default 0x00) Test Modes: Reserved for Winbond. W83977ATF/W83977ATG Publication Release Date: May 2006 - 135 - Revision 0.6 ...
Page 144
... FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP The internal pull-up resistors of FDC are turned on.(Default The internal pull-up resistors of FDC are turned off. W83977ATF/W83977ATG DMA0 DMA1 DMA2 DMA3 - 136 - ...
Page 145
... Bit Boot Floppy = 00 FDD FDD FDD FDD D Bit Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Bit Density Select = 00 Normal (Default Normal = Forced to logic Forced to logic 0) W83977ATF/W83977ATG Publication Release Date: May 2006 - 137 - Revision 0.6 ...
Page 146
... FDD0 Selection: Bit 7 : Reserved. Bit 6 : Precomp. Disable Disable FDC Precompensation Enable FDC Precompensation. Bit 5 : Reserved. Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 Specifical application = 10 2 Meg Tape = 11 Reserved W83977ATF/W83977ATG DRATE1 DRATE0 138 - SELDEN 1 1 ...
Page 147
... DRIVE RATE TABLE SELECT DRTS1 DRTS0 Note: Refer to CRF2 for SELDEN value in the cases when CRF0, bit0=1. TABLE B DMOD0 DMOD1 DRVDEN0(PIN W83977ATF/W83977ATG DATA RATE SELECTED DATA RATE DRATE1 DRATE0 MFM 1 1 1Meg 0 0 500K 0 1 300K 1 0 250K 1 1 1Meg 0 0 500K ...
Page 148
... IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP. Bit [6:3] : ECP FIFO Threshold. Bit Parallel Port Mode = 100 Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode W83977ATF/W83977ATG - 140 - ...
Page 149
... Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. W83977ATF/W83977ATG Publication Release Date: May 2006 - 141 - Revision 0.6 ...
Page 150
... Bit [3:0] : These bits select IRQ resource for MINT (PS2 Mouse) CRF0 (Default 0x83) Bit KBC clock rate selection = 00 Select 6MHz as KBC clock input Select 8MHz as KBC clock input Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. W83977ATF/W83977ATG - 142 - ...
Page 151
... CR75 (Default 0x04) Bit 7-3 : Reserved. Bit 2-0 : These bits select DRQ resource for TX of UART C. = 0x00 = 0x01 = 0x02 = 0x03 = 0x04-0x07 W83977ATF/W83977ATG DMA0 DMA1 DMA2 DMA3 No DMA active DMA0 DMA1 DMA2 DMA3 No DMA active - 143 - Publication Release Date: May 2006 ...
Page 152
... These two registers select GP15 alternate function Primary I/O base address [0x100:0xFFF byte boundary; they are available as you set GP15 alternate function (General Purpose Write Decode). CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for GP10 as you set GP10 alternate function (Interrupt Steering). W83977ATF/W83977ATG - 144 - ...
Page 153
... IRQ Filter Select = 1 Debounce Filter Enabled = 0 Debounce Filter Bypassed Bit 3 : Select Function Select Alternate Function: Interrupt Steering Select Basic I/O Function. Bit 2 : Reserved. Bit 1 : Polarity Invert Invert. Bit 0 : In/Out selection Input Output. W83977ATF/W83977ATG Publication Release Date: May 2006 - 145 - Revision 0.6 ...
Page 154
... Select 1st alternate function: General Purpose Address Decoder(Active Low when Bit 1= 0, Decode two byte address Select 2nd alternate function: Keyboard Inhibit (P17 Reserved Bit 2 : Reserved. Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output CRE5 (GP15, Default 0x01) Bit Reserved. Bit Select Function Select Basic I/O function. W83977ATF/W83977ATG - 146 - ...
Page 155
... In/Out: 1: Input, 0: Output TABLE C WDT_CTRL1* BIT[1 *Note: 1). Regarding to the contents of WDT_CTR1 and WDT_CTRL0, please refer to CRF3 and CRF4 in Logic Device 8. 2). Continuous high or low depends on the polarity bit of GP13 or GP17 configure registers. W83977ATF/W83977ATG WDT_CTRL0* BIT[3] WDT_CTRL1 BIT[ 147 - POWER LED STATE ...
Page 156
... CRE8 (GP20, Default 0x01) Bit Reserved. Bit Select Function Select basic I/O function = 01 Reserved = 10 Select alternate function: Keyboard Reset (connected to KBC P20 Reserved Bit 2 : Int Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output W83977ATF/W83977ATG - 148 - ...
Page 157
... Reserved. Bit Select Function Select Basic I/O function = 01 Reserved = 10 Select 2nd alternate function: Keyboard P15 I Reserved Bit 2 : Int Enable Common IRQ = 0 Disable Common IRQ Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output W83977ATF/W83977ATG Publication Release Date: May 2006 - 149 - Revision 0.6 ...
Page 158
... Disable Common IRQ Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output CRF0 (Default 0x00) Debounce Filter Enable or Disable for General Purpose I/O Combined Interrupt. The Debounce Filter can reject a pulse with 1ms width or less. Bit Reserved Bit Common IRQ Filter Select W83977ATF/W83977ATG - 150 - ...
Page 159
... Watch Dog Timer is not affected by Keyboard interrupt Bit 0 : Reserved. CRF4 (WDT_CTRL1, Default 0x00) Watch Dog Timer Control Register #1 Bit Reserved Bit 3 : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/ Enable = 0 Disable W83977ATF/W83977ATG Publication Release Date: May 2006 - 151 - Revision 0.6 ...
Page 160
... CR70 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for GP30 as you set GP30 alternate function (Interrupt Steering). CR72 (Default 0x00) Bit Reserved. Bit These bits select IRQ resource for GP31 as you set GP31 alternate function (Interrupt Steering). W83977ATF/W83977ATG - 152 - ...
Page 161
... Select Basic I/O Function. Bit 2 : Reserved. Bit 1 : Polarity Invert Invert. Bit 0 : In/Out selection Input Output. CRE2 (GP32, Default 0x01) Bit Reserved. Bit 3 : Select Function Select Alternate Function: General Purpose Address Decode Select Basic I/O Function. W83977ATF/W83977ATG Publication Release Date: May 2006 - 153 - Revision 0.6 ...
Page 162
... CRE5 (GP35, Default 0x01) Bit Reserved. Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output CRE6 (GP36, Default 0x01) Bit Reserved. Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output CRE7 (GP37, Default 0x01) Bit Reserved. Bit 1 : Polarity: 1: Invert Invert Bit 0 : In/Out: 1: Input, 0: Output W83977ATF/W83977ATG - 154 - ...
Page 163
... DIS-PANSWIN. Disable panel switch input to turn system power supply on PANSWIN is wire-ANDed and connected to PANSWOUT . = 1 PANSWIN is blocked and can not affect PANSWOUT . Bit 6 : ENKBWAKEUP. Enable Keyboard to wake-up system via PANSWOUT . = 0 Disable Keyboard wake-up function Enable Keyboard wake-up function. W83977ATF/W83977ATG Publication Release Date: May 2006 - 155 - Revision 0.6 ...
Page 164
... PANSW_STS. The Panel switch event is caused by PANSWIN . This bit is cleared by reading this register. Bit 1 : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. Bit 2 : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. W83977ATF/W83977ATG is ignored). - 156 - ...
Page 165
... FDCPME. FDC power management enable disable the auto power management functions enable the auto power management functions provided CRF0.bit7 (CHIPPME) is also set to 1. Bit 1 : URAPME. UART A power management enable disable the auto power management functions. W83977ATF/W83977ATG Publication Release Date: May 2006 - 157 - Revision 0.6 ...
Page 166
... UART B is now in the working state UART B is now in the sleeping state due to no UART A access, no IRQ, the receiver is now waiting for a start bit, the transmitter shift register is now empty, and no transition on MODEM control input lines in a preset expiry time period. W83977ATF/W83977ATG - 158 - ...
Page 167
... These bits indicate the IRQ status of the individual device. The device's IRQ status bit is set by their source device and is cleared by writing a 1. Writing a 0 has no effect. Bit 7 : Reserved. Return zero when read. Bit 6 : IRIRQSTS. IR IRQ status. Bit 5 : MOUIRQSTS. MOUSE IRQ status. W83977ATF/W83977ATG start bit. Publication Release Date: May 2006 - 159 - Revision 0.6 ...
Page 168
... SMI interrupt due to printer port's IRQ enable the generation of an SMI interrupt due to printer port's IRQ. Bit 2 : FDCIRQEN disable the generation of an SMI interrupt due to FDC's IRQ enable the generation of an SMI interrupt due to FDC's IRQ. W83977ATF/W83977ATG - 160 - ...
Page 169
... SMI logic, setting this bit enables the SMI interrupt to be generated on the pin SMI . If this bit is cleared, only the IRQ status bit in CRF3 is set and no SMI interrupt is generated on the pin SMI . = 0 Disable SMI = 1 Enable SMI CRFE, FF (Default 0x00) Reserved. Reserved for Winbond test. W83977ATF/W83977ATG Publication Release Date: May 2006 - 161 - Revision 0.6 ...
Page 170
... TTL level bi-directional pin with source-sink capability Input Low Voltage VIL Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH Input Low Leakage ILIL W83977ATF/W83977ATG RATING -0.5 to 7.0 -0.5 to VDD+0.5 4 +70 -55 to +150 = 0V) SS MIN. TYP. MAX. UNIT 2 ...
Page 171
... TTL level bi-directional pin with source-sink capability 12t Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Input High Leakage I LIH Input Low Leakage I LIL W83977ATF/W83977ATG MIN. TYP. MAX. 0.3xVDD 0.7xVDD 0.4 3 0.3xVDD 0.7xVDD 0.4 3 0.3xVDD 0.7xVDD 0.4 3.5 ...
Page 172
... Input High Leakage I LIH Input Low Leakage I LIL Input Low Vt- Threshold Voltage Input High Vt+ Threshold Voltage Hystersis VTH Input High Leakage ILIH Input Low Leakage ILIL W83977ATF/W83977ATG MIN. TYP. MAX. 0.8 2.0 0.4 2 0.4 2.4 0.4 2.4 0.4 0.4 0.8 2.0 ...
Page 173
... Hystersis Input High Leakage Input Low Leakage IN - TTL level Schmitt-triggered input pin with internal pull-up resistor tsu Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage W83977ATF/W83977ATG SYM. MIN. TYP. MAX. V 0.7xV IL V 0.7xV IH DD ...
Page 174
... DACK DRQ to delay DACK width IOR DRQ delay from IOW DRQ delay from IOW IOR or response time from DRQ TC width RESET width W83977ATF/W83977ATG SYM. TEST MIN. CONDITIONS TAR TAR TRR CL = 100 pf TFD TDH CL = 100 100 pf TDF TRI TAW TWA TWW TDW ...
Page 175
... IOR Delay from to Reset Interrupt IOR Delay from to Output Set Interrupt Delay from Modem Input IOR Reset Interrupt Delay from Interrupt Active Delay Interrupt Inactive Delay Baud Divisor W83977ATF/W83977ATG SYM. TEST CONDITIONS TIDX 0.5/0.9 TDST 1.0/1.6 TSTD 24/40/48 TSTP 6.8/11.5 TSC ...
Page 176
... Command Asserted to PD Valid Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out WAIT PD Valid to Deasserted WAIT PD Hi-Z to Deasserted W83977ATF/W83977ATG SYM. t1 Delay from SYM Asserted ...
Page 177
... Command Asserted WAIT Asserted to Command Asserted WAIT Deasserted to Command Deasserted WAIT Command Asserted to Deasserted Time out WAIT Command Deasserted to IOW WRITE Deasserted to Deasserted and PD invalid W83977ATF/W83977ATG SYM. Asserted Deasserted t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 ...
Page 178
... Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted 15.3.8 ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83977ATF/W83977ATG SYMBOL MIN. t1 600 t2 600 t3 450 t4 ...
Page 179
... Time from inactive CLK transition, used to time when the auxiliary device sample DATA T25 Time of inhibit mode T26 Time from rising edge of CLK to DATA transition T27 Duration of CLK inactive T28 Duration of CLK active T29 Time from DATA transition to falling edge of CLK W83977ATF/W83977ATG DESCRIPTION - 171 - MIN. MAX. UNIT ...
Page 180
... GPIO Timing Parameters SYMBOL t Write data to GPIO update WGO t SWITCH pulse width SWP Note: Refer to Microprocessor Interface Timing for Read Timing. W83977ATF/W83977ATG PARAMETER - 172 - MIN. MAX. UNIT 300(Note msec ...
Page 181
... Processor Write Operation SA0-SA9 AEN TAW DACK IOW D0-D7 IRQ DMA Operation TAM DRQ DACK TMA TMRW IOW or IOR TMW (IOW) TMR (IOR) W83977ATF/W83977ATG TRA TRR TDH TDF TR TWA TWW TWD TDW TWI DIR TMCY TAA STEP - 173 - Write Date WD TWDD ...
Page 182
... IRQ3 or IRQ4 IOR (READ RECEIVER BUFFER REGISTER) SERIAL OUT STAR (SOUT) THRS IRQ3 or IRQ4 THR IOW TSI (WRITE THR) IOR (READ TIR) W83977ATF/W83977ATG Receiver Timing STAR DATA BITS (5-8) Transmitter Timing DATA (5-8) THR - 174 - PARITY STOP TSINT TRINT STAR PARITY ...
Page 183
... Modem Control Timing IOW (WRITE MCR) RTS,DTR │ CTS,DSR │ DCD │ → ← │ IRQ3 or IRQ4 IOR (READ MSR) RI ACK IRQ7 W83977ATF/W83977ATG MODEM Control Timing │ │ │ → ← TMWO │ │ │ │ │ ? │ │ → │ ...
Page 184
... Parallel Port 16.3.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ W83977ATF/W83977ATG 176 - ...
Page 185
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT W83977ATF/W83977ATG t18 t17 t21 t25 t27 t26 - 177 - t15 t19 t20 t28 Publication Release Date: May 2006 ...
Page 186
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR W83977ATF/W83977ATG t10 t11 t13 t15 t16 t17 t18 t19 t20 - 178 - t12 t14 t21 ...
Page 187
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT W83977ATF/W83977ATG t18 t21 t25 t26 t27 - 179 - t15 t19 t20 t28 Publication Release Date: May 2006 Revision 0.6 ...
Page 188
... EPP Data or Address Write Cycle (EPP Version 1.7) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 16.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY W83977ATF/W83977ATG t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| t6 >| - 180 - t22 t22 t4 > ...
Page 189
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 16.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD W83977ATF/W83977ATG 181 - Publication Release Date: May 2006 Revision 0.6 ...
Page 190
... A2, CSB WRB D0~D7 GA20 OUTPUT PORT FAST RESET PULSE RC FE COMMAND 16.4.2 Read Cycle Timing A2,CSB AEN RDB D0-D7 16.4.3 Send Data to K/B CLOCK (KCLK) T12 SERIAL DATA START (KDAT) W83977ATF/W83977ATG T1 T3 ACTIVE T7 DATA ACTIVE T10 T11 DATA OUT T13 T14 ...
Page 191
... CLOCK (KCLK) T15 SERIAL DATA START (T1) T20 16.4.5 Input Clock CLOCK CLOCK T21 16.4.6 Send Data to Mouse MCLK T25 MDAT START Bit 16.4.7 Receive Data from Mouse MCLK T29 MDAT START W83977ATF/W83977ATG T14 T13 T23 T24 T22 T26 T27 T28 D5 D0 ...
Page 192
... GPIO Write Timing Diagram A0-A15 IOW D0-7 GPIO10-17 GPIO20-25 16.6 Master Reset (MR) Timing Vcc MR W83977ATF/W83977ATG VALID VALID PREVIOUS STATE tVMR - 184 - VALID tWGO ...
Page 193
... PD5 19 6 DCH2/PD4 18 RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram W83977ATF/W83977ATG JP13 - 185 - JP 13A DCH2 33 34 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 ...
Page 194
... STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram 17.3 Four FDD Mode W83977ATF DSA DSB MOA MOB W83977ATF/W83977ATG JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 186 - JP 13A DCH2 34 33 HEAD2 ...
Page 195
... ORDERING INFORMATION PART NO. W83977ATF-AW W83977ATG-AW W83977ATF/W83977ATG KBC FIRMWARE TM AMIKEY -2 TM Lead-free package AMIKEY -2 Publication Release Date: May 2006 - 187 - REMARKS Revision 0.6 ...
Page 196
... W 83977ATG-AW © AM. MEGA. 87-96 719AC27039520 1st line: Winbond logo 2nd line: the type number: W83977ATG-AW; G means lead-free package. 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: Tracking code 719 : packages made in '97, week assembly house ID; A means ASE, S means SPIL revision ...
Page 197
... PACKAGE DIMENSIONS (128-pin QFP 102 103 128 See Detail F y Seating Plane W83977ATF/W83977ATG Detail F - 189 - Dimension in mm Dimension in inch Symbol Min Nom Min Nom Max A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.10 0.20 0.30 0.004 ...
Page 198
... Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83977ATF/W83977ATG Important Notice - 190 - ...