W83627HF-AW Nuvoton Technology Corporation of America, W83627HF-AW Datasheet
W83627HF-AW
Specifications of W83627HF-AW
Available stocks
Related parts for W83627HF-AW
W83627HF-AW Summary of contents
Page 1
... W83627HF/F W83627HG/G Winbond LPC I/O Date： 2006/06/09 Revision： 2.27 ...
Page 2
... W83627HF/F, W83627HG/G Data Sheet Revision History VERSION DATE 0.50 09/25/98 88-93,102,105, 0.51 11/10/98 139,151,153 0.52 01/11/99 90-93;113-115 90,91,113-115, 0.53 07/26/99 119-123,133,136, 137,140,141 1.0 11/14/00 All 2.0 11/01/02 All 2.1 03/07/ P74 ~ P76 2.2 04/09/03 2. P3,P90,P111 3. P6~P7 2.21 02/03/04 121 12,13,21,23,39,4 2.22 ...
Page 3
... Table of Content- 1. GENERAL DESCRIPTION ......................................................................................................... 1 2. FEATURES ................................................................................................................................. 3 3. BLOCK DIAGRAM FOR W83627F............................................................................................. 6 4. BLOCK DIAGRAM FOR W83627HF .......................................................................................... 7 5. PIN CONFIGURATION ............................................................................................................... 8 6. PIN DESCRIPTION................................................................................................................... 12 6.1 LPC Interface ............................................................................................................... 13 6.2 FDC Interface............................................................................................................... 14 6.3 Multi-Mode Parallel Port............................................................................................... 15 6.4 Serial Port Interface ..................................................................................................... 21 6.5 KBC Interface............................................................................................................... 22 6.6 ACPI Interface.............................................................................................................. 22 6 ...
Page 4
... Parallel Port Extension FDD ...................................................................................... 118 11.2 Parallel Port Extension 2FDD .................................................................................... 118 11.3 Four FDD Mode ......................................................................................................... 119 12. ORDERING INSTRUCTION ................................................................................................... 120 13. HOW TO READ THE TOP MARKING.................................................................................... 120 14. PACKAGE DIMENSIONS ....................................................................................................... 121 15. APPENDIX A ： DEMO CIRCUIT .......................................................................................... 122 W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 - iii - Revision 2.27 ...
Page 5
... GENERAL DESCRIPTION The W83627HF and W83627F are evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC（Low Pin Count）interface, which will be supported in the next generation Intel chip-set. This interface as its name suggests is to provide an economical imple- mentation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart ...
Page 6
... PC game control devices, They are very important for a en- tertainment or consumer computer. Only the W83627HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly ...
Page 7
... Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs • MIDI compatible • Fully programmable serial-interface characteristics： ─ 8-bit characters ─ Even, odd or no parity bit generation/detection ─ stop bits generation W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 - 3 - Revision 2.27 ...
Page 8
... Support binary and BCD arithmetic • 6 MHz, 8 MHz, 12 MHz MHz operating frequency Game Port • Support two separate Joysticks • Support every Joystick two axis （X,Y） and two button （A,B） controllers W83627HF -2,or customer code with 2K bytes of program ...
Page 9
... CIR Wake-Up by programmable keys • On Now Wake-Up from all of the ACPI sleeping states （S1-S5） Hardware Monitor Functions （ Only for W83627HF） • 5 VID input pins for CPU Vcore identification • 3 thermal inputs from optionally remote thermistors or 2N3904 transistors or Pentium （ ...
Page 10
... BLOCK DIAGRAM FOR W83627F LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock W83627HF/ F/ HG/ G LPC Interface Game FDC Port MIDI URA, B GPIO IR KBC CIR ACPI PRT - 6 - Floppy drive interface signals Serial port A, B ...
Page 11
... BLOCK DIAGRAM FOR W83627HF LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Joystick interface signals MSI MSO General-purpose I/O pins Keyboard/Mouse data and clock Hardware monitor channel and Vref W83627HF/ F/ HG/ G LPC Interface Game FDC Port MIDI URA, B GPIO IR KBC CIR HM PRT ACPI ...
Page 12
... GPY2/P16/GP14 GPX2/P15/GP13 125 126 GPX1/P14/GP12 127 GPSB1/P13/GP11 128 GPSA1/P12/GP10 W83627F W83627HF SUSLED/GP35 KDAT 63 62 KCLK 61 VSB KBRST 60 59 A20GATE KBLOCK# 58 RIA DCDA# VSS 55 54 SOUTA 53 SINA 52 DTRA# 51 RTSA# 50 DSRA# 49 CTSA# 48 VCC 47 STB# 46 AFD# 45 ERR# 44 INIT# 43 SLIN# 42 PD0 41 PD1 40 PD2 39 PD3 ...
Page 13
... GPSA2/GP17 GPSA2/GP17 122 122 122 GPSB2/GP16 GPSB2/GP16 123 123 123 GPY1/GP15 GPY1/GP15 124 124 124 GPY2/P16/GP14 GPY2/P16/GP14 GPX2/P15/GP13 GPX2/P15/GP13 125 125 125 126 126 126 GPX1/P14/GP12 GPX1/P14/GP12 127 127 127 GPSB1/P13/GP11 GPSB1/P13/GP11 GPSA1/P12/GP10 GPSA1/P12/GP10 128 128 128 W83627HF ...
Page 14
... PIN CONFIGURATION of W83627HF and W83627HG VTIN2 103 104 VTIN1 OVT# 105 VID4 106 107 VID3 108 VID2 VID1 109 110 VID0 FANIO3 111 FANIO2 112 113 FANIO1 VCC 114 115 FANPWM2 116 FANPWM1 117 VSS 118 BEEP 119 MSI/GP20 120 MSO/IRQIN0 ...
Page 15
... GPSA2/GP17 GPSA2/GP17 122 122 122 GPSB2/GP16 GPSB2/GP16 123 123 123 GPY1/GP15 GPY1/GP15 124 124 124 GPY2/P16/GP14 GPY2/P16/GP14 125 125 125 GPX2/P15/GP13 GPX2/P15/GP13 126 126 126 GPX1/P14/GP12 GPX1/P14/GP12 127 127 127 GPSB1/P13/GP11 GPSB1/P13/GP11 128 128 128 GPSA1/P12/GP10 GPSA1/P12/GP10 W83627HF ...
Page 16
... O 3.3V output pin with 24 mA source-sink capability 24p3 OD Open-drain output pin with 12 mA sink capability 12 OD24 Open-drain output pin with 24 mA sink capability OD12p3 3.3V open-drain output pin with 12 mA sink capability W83627HF/ F/ HG/ G DESCRIPTION - 12 - ...
Page 17
... LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. 32khz clock input, for CIR only W83627HF/ F/ HG/ G FUNCTION Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 18
... L0-CRF0（FIPURDWN）. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin is pulled up internally ohm resistor. The resistor can be disabled by bit 7 of L0-CRF0 （FIPURDWN） W83627HF/ F/ HG/ G FUNCTION ...
Page 19
... EXTENSION FDD MODE： This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC W83627HF/ F/ HG/ G FUNCTION FUNCTION Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 20
... Parallel port data bus bit 7. Refer to the description of the par- allel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE： 12 This pin is a tri-state output. EXTENSION 2FDD MODE： This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC W83627HF/ F/ HG/ G FUNCTION ...
Page 21
... This pin is for Extension FDD B; its function is the same as the RDATA# pin of FDC pulled high internally. EXTENSION 2FDD MODE： RDATA2# This pin is for Extension FDD A and B; its function is the same as the RDATA# pin of FDC pulled high internally W83627HF/ F/ HG/ G FUNCTION Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 22
... EXTENSION FDD MODE： ts This pin is for Extension FDD B; its function is the same as the INDEX# pin of FDC pulled high internally. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the INDEX# pin of FDC pulled high internally W83627HF/ F/ HG/ G FUNCTION ...
Page 23
... This pin is for Extension FDD B; its function is the same as the HEAD# pin of FDC. EXTENSION 2FDD MODE： This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC W83627HF/ F/ HG/ G FUNCTION Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 24
... An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the defi- nition of this pin in ECP and EPP mode. EXTENSION FDD MODE： This pin is a tri-state output EXTENSION 2FDD MODE： This pin is a tri-state output W83627HF/ F/ HG/ G FUNCTION ...
Page 25
... Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 26
... For UD-Mask A-version, this pin is TTL level. Panel Switch Output. This signal is used for Wake-Up system 12 from S5 state. This pin is pulse output, active low Panel Switch Input. This pin is high active with an internal pull down resistor. Battery voltage input W83627HF/ F/ HG/ G FUNCTION FUNCTION ...
Page 27
... Hardware Monitor Interface （For W83627HF only, all these pins in W83627F are NC.） SYMBOL PIN I CASEOPEN# -5VIN 94 AIN -12VIN 95 AIN +12VIN 96 AIN +3.3VIN 98 AIN VCOREB 99 AIN VCOREA 100 AIN VREF 101 PWR VTIN3 102 AIN VTIN2 103 AIN VTIN1 104 AIN ...
Page 28
... Active-low, Joystick II switch input 1. （Default） General purpose I/O port 1 bit 1. Alternate Function Output： KBC P13 I/O port. Active-low, Joystick I switch input 1. （Default） General purpose I/O port 1 bit 0. Alternate Function Output： KBC P12 I/O port W83627HF/ F/ HG/ G FUNCTION ...
Page 29
... MIDI serial data input. Schmitt trigger input with internal pull-up t resistor. General purpose I/O port 2 bit 1. 12t Serail Bus Clock.（availiable for W83627HF only） General purpose I/O port 2 bit 2. 12t Serial Bus Data.（availiable for W83627HF only） 12ts General purpose I/O port 2 bit 3. ...
Page 30
... Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground ref- erence for all analog inputs.. Ground W83627HF/ F/ HG/ G FUNCTION （Default） FUNCTION ...
Page 31
... The first interface uses LPC Bus to access which the ports of low byte （bit2~bit0） are defined in the port 5h and 6h. The other higher bits of these ports is set by W83627HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following： ...
Page 32
... Register Register Port 6h Port 6h Data Data Register Register Figure 8.1 ： ISA interface access diagram W83627HF/ F/ HG/ G Configuration Register Configuration Register 40h 40h SMI# Status/Mask Registers SMI# Status/Mask Registers 41h, 42h, 44h, 45h 41h, 42h, 44h, 45h VID<3:0>/Fan Divisor Register VID< ...
Page 33
... The second interface uses I C Serial Bus. W83627HF hardware monitor has three serial bus address. That is, the first address defined at CR[48h] can read/write all registers excluding Bank 1 and Bank 2 temperature sensor 2/3 registers. The second address defined at CR[4Ah] bit2-0 only read/write tem- perature sensor 2 registers, and the third address defined at CR[4Ah] bit6-4 only can access （ ...
Page 34
... MSB Data Byte R Ack by 782D ... ... Ack Frame 4 by 782D MSB Data Byte R Ack by 782D Data Byte - 30 - W83627HF/ F/ HG/ G ） ... ... Ack by Frame 3 Master LSB Data Byte Temp, TOS, THYST （ ） Ack Frame 2 by 782D Pointer Byte ... ... Ack by Frame 5 Master ...
Page 35
... Ack Frame 2 by 782D MSB Data Byte R Ack by 782D ... ... Ack Frame 4 by 782D MSB Data Byte R Ack by 782D Data Byte - 31 - W83627HF ... ... Ack by Frame 3 Master LSB Data Byte Ack Frame 2 by 782D Pointer Byte ... ... Ack by Frame 5 Master LSB Data Byte ...
Page 36
... ADC. The Pin 97 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83627HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage ...
Page 37
... The Pin 61 is connected to 5VSB voltage. W83627HF monitors this voltage and the internal two serial resistors are 17K Ω and 33K Ω so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage. 7.3.2 Monitor negative voltage： The negative voltage should be connected two series resistors and a positive voltage VREF （is equal to 3.6V） ...
Page 38
... Figure 8.3. The pin of Pentium II nected to power supply ground （GND） and the pin D+ is connected to pin VTINx in the W83627HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the by- pass capacitor C=3300pF should be added to filter the high frequency noise. The transistor 2N3904 should be connected to a form with a diode, that is, the Base （ ...
Page 39
... That provides very low speed fan counter such as power supply fan. The fol- lowed table is an example for the relation of divisor, PRM, and count. R=30K, 1% C=3300pF R=30K C=3300pF D- Figure. 8.3 6 × Count × RPM Divisor × RPM × Count Divisor - 35 - W83627HF/ F/ HG/ G VREF VTINx W83627HF VTINx Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 40
... Pull-up resister > 1K +12V FAN Out Pin 111-113 Fan Input GND 3.9V Zener W83627HF FAN Connector Fan with Tach Pull-Up to +12V and Zener Clamp W83627HF/ F/ HG/ G Table 2. TIME PER COUNTS REVOLUTION 6.82 ms 153 13.64 ms 153 27.27 ms 153 54.54 ms 153 109.08 ms 153 218 ...
Page 41
... Fan speed control The W83627HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be pro- grammed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be repre- sented as follows. − ...
Page 42
... SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. （See Figure 8.7） Figure. 8.6 SMI# Two-Times Interrupt Mode Figure. 8.7 Two-Times Interrupt Mode - 38 - W83627HF/ F/ HG/ G ...
Page 43
... Temperature 1 SMI# modes The W83627HF temperature sensor 1 SMI# interrupt has two modes （1）Comparator Interrupt Mode Setting the T （Temperature Hysteresis） limit to 127°C will set temperature sensor 1 SMI# HYST to the Comparator Interrupt Mode. Temperature exceeds T an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an in- ...
Page 44
... Temperature 2, 3 SMI# modes： The W83627HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is pro- grammed at CR[4Ch] bit 6. （1）Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conver- sion has completed ...
Page 45
... OVT# interrupt mode The W83627HF OVT# signal is only related to temperature sensor 2 and 3（VTIN2 / VTIN3）. They have two modes： （1）Comparator Mode： Setting Bank1/2 CR[52h] bit will set OVT# signal to comparator mode. Temperature ex- ceeding TO causes the OVT# output activated until the temperature is less than THYST.（See Figure 8.12） ...
Page 46
... Bit7： Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83627HF hardware monitor without interfering with each other or a Serial Bus driver the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. ...
Page 47
... Reserved ; <2：0> = 000 - 43 - W83627HF/ F/ HG/ G NOTES Auto-increment to the address of Interrupt Status Register 2 af- ter a read or write to Port x6h. Auto-increment to the address of SMIÝ Mask Register 2 after a read or write to Port x6h. Auto-increment to the address ...
Page 48
... Bank1 50h-56h Bank2 50h-56h Bank4 50h-5Dh Port x6h 00h Read/write 8 bits W83627HF/ F/ HG/ G NOTES Auto-increment to the next loca- tion after a read or write to Port x6h and stop at 1Fh. Auto-increment to the next loca- tion after a read or write to Port x6h and stop at 7Fh. Data ...
Page 49
... Power on Default Value： Attribute： Size： 40h 01h Read/write 8 bits START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION 41h 00h Read Only 8 bits W83627HF/ F/ HG/ G VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 50
... Bit 2： A “1” indicates a High or Low limit of -5VIN has been exceeded. Bit 1： A “1” indicates a High or Low limit of -12VIN has been exceeded. Bit 0： A “1” indicates a High or Low limit of +12VIN has been exceeded. 42h 00h Read Only 8 bits +12VIN -12VIN -5VIN FAN3 Chassis Intrusion Temp3 Reserved Reserved - 46 - W83627HF/ F/ HG/ G ...
Page 51
... Bit 5-0： A one disables the corresponding interrupt status bit for SMI interrupt. 43h 00h Read/Write 8 bits 44h 00h Read/Write 8 bits +12VIN -12VIN -5VIN FAN3 Chassis Intrusion TEMP3 Reserved Reserved - 47 - W83627HF/ F/ HG/ G VCOREA VCOREB +3.3VIN +5VIN TEMP1 TEMP2 FAN1 FAN2 Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 52
... Bit 7： Clear Chassis Intrusion Event. Write “1” will make Hardware Monitor Register Index 42, bit 4 cleared to “0”）. This bit self clears after clearing Chassis Intrusion event. For W83627HF A Version, Clear Chassis Intrusion Event has been changed form this bit to LDA CRE6[6]. ...
Page 53
... Note： This location stores the number of counts of the internal clock per revolution. FAN2 reading 69h Note： This location stores the number of counts of the internal clock per revolution W83627HF/ F/ HG/ G Serial Bus Address Reserved DESCRIPTION Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 54
... FAN2 Fan Count Limit 7Ch Note： the number of counts of the internal clock for the Low Limit of the fan speed. FAN3 Fan Count Limit 7Dh Note： the number of counts of the internal clock for the Low Limit of the fan speed. Reserved - 50 - W83627HF/ F/ HG/ G DESCRIPTION ...
Page 55
... Bit 2-0： Temperature 2 Serial Bus Address. The serial bus address is 1001xxx. Where xxx are defined in these bits. 49h <7：1> is 000,0001 binary, <0> is mapped to VID <4> 8 bits 4Ah 01h Read/Write 8 bits W83627HF/ F/ HG/ G VID4 DID<6:0> I2CADDR2 I2CADDR2 I2CADDR2 DIS_T2 I2CADDR3 I2CADDR3 I2CADDR3 DIS_T3 Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 56
... Default. Pin 3 （CLKIN） select 24M Hz clock. <3：2> Pin 3 （CLKIN） select 48M Hz clock . <3：2> Reserved. Pin3 no clock input. Bit 1-0：Reserved. User defined. 4Bh 44h Read/Write 8 bits Reserved Reserved CLKINSEL CLKINSEL ADCOVSEL ADCOVSEL FAN3DIV_B0 FAN3DIV_B1 - 52 - W83627HF/ F/ HG/ G ...
Page 57
... OVT1 output through pin OVT#. Bit 2： Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. Default 0. Bit 1： Reserved. Bit 0： Reserved. 4Ch 00h Read/Write 8 bits Reserved Reserved OVTPOL DIS_OVT1 DIS_OVT2 Reserved T23_INTMode Reserved - 53 - W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 58
... Bit 0： FAN 1 Input Control. Set to 1, pin 20 acts as FAN clock input, which is default value. Set to 0, this pin 20 acts as FAN control signal and the output value of FAN control is set by this register bit 1. 4Dh 15h Read/Write 8 bits FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 RESERVED DIS_ABN - 54 - W83627HF/ F/ HG/ G ...
Page 59
... Bit 15-8： Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0： Vendor ID Low Byte if CR4E.bit7=0. Default A3h. 4Eh 80h Read/Write 8 bits BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS 4Fh <15：0> = 5CA3h Read Only 16 bits W83627HF/ F/ HG/ G VIDH VIDL Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 60
... Bit 1： Enable BEEP output from VCOREB. Write 1, enable BEEP output, which is default value. Bit 0： Enable BEEP Output from VCOREA if the monitor value exceed the limits value. Write 1, en- able BEEP output, which is default value 56h 00h Read/Write 8 bits EN_VCA_BP EN_VCB_BP EN_V33_BP EN_V5_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP - 56 - W83627HF/ F/ HG/ G ...
Page 61
... Bit 0： Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default is 0, which is disable BEEP output EN_V12_BP EN_NV12_BP EN_NV5_BP EN_FAN3_BP EN_CASO_BP EN_T3_BP Reserved EN_GBP - 57 - W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 62
... Bit 4： Temperature sensor diode 1. Set to 1, select Pentium II compatible Diode. Set select 2N3904 Bi- polar mode. Bit 3-0： Reserved 58h 21h Read Only 8 bits 59h 70h Read/Write 8 bits Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 SELPIIV3 Reserved - 58 - W83627HF/ F/ HG/ G CHIPID ...
Page 63
... Power on default value： Attribute： Size： Bit 7： PWMOUT2 duty cycle control. Write FF, Duty cycle is 100%, Write 00, Duty cycle is 0%. 5Ah FFh Read/Write 8 bits 5Bh FFh Read/Write 8 bits W83627HF/ F/ HG/ G PWM1_DUTY PWM2_DUTY Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 64
... Hz <2：0> = 001： 23.43K Hz （Default） <2：0> = 010： 11.72K Hz <2：0> = 011： 5.85K Hz <2：0> = 100： 2.93K Hz 5Ch 11h Read/Write 8 bits PWM1CLKSEL PWM1CLKSEL PWM1CLKSEL Reserved PWM2CLKSEL PWM2CLKSEL PWM2CLKSEL Reserved - 60 - W83627HF/ F/ HG/ G ...
Page 65
... Bit 0： Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83627HF hardware monitor. Fan divisor table ： ...
Page 66
... Bit 7： Temperature <8：1> of sensor 2, which is high byte. VTIN2 Reading（Low Byte）- Index 51h （Bank 1） Register Location： 51h Attribute： Read Only Size： 8 bits 7 Bit 7： Temperature <0> of sensor2, which is low byte. Bit 6-0： Reserved TEMP2<0> W83627HF/ F/ HG/ G TEMP2<8:1> Reserved ...
Page 67
... Size： Bit 7-0： Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 52h 00h 8 bits STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved 53h 4Bh Read/Write 8 bits W83627HF/ F/ HG/ G THYST2<8:1> Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 68
... VTIN2 Over-temperature（High Byte）Register - Index 55h （Bank 1） Register Location： Power on Default Value Attribute： Size： Bit 7-0： Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 54h 00h Read/Write 8 bits THYST2<0> 55h 50h Read/Write 8 bits W83627HF/ F/ HG/ G Reserved TOVF2<8:1> ...
Page 69
... VTIN3 Reading（High Byte）Register - Index 50h （Bank 2） Register Location： 50h Attribute： Read Only Size： 8 bits 7 Bit 7-0： Temperature <8：1> of sensor 2, which is high byte. 56h 00h Read/Write 8 bits W83627HF/ F/ HG/ G Reserved TOVF2<0> TEMP2<8:1> Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 70
... Bit 1： Read/Write - OVT# Interrupt Mode select. This bit default is set to 0, which is Compared Mode. When set to 1, Interrupt Mode will be selected. Bit 0： Read/Write - When set to 1 the sensor will stop monitor TEMP2<0> 52h 00h Read/Write 8 bits STOP3 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved - 66 - W83627HF/ F/ HG/ G Reserved ...
Page 71
... Register Location： Power on Default Value： Attribute： Size： 7 Bit 7： Hysteresis temperature bit 0, which is low Byte. Bit 6-0： Reserved. 53h 4Bh Read/Write 8 bits 54h 00h Read/Write 8 bits THYST3<0> W83627HF/ F/ HG/ G THYST3<8:1> Reserved Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 72
... VTIN3 Over-temperature（Low Byte）Register - Index 56h（Bank 2） Register Location： Power on Default Value： Attribute： Size： 7 Bit 7： Over-temperature bit 0, which is low Byte. Bit 6-0： Reserved. 55h 50h Read/Write 8 bits 56h 00h Read/Write 8 bits TOVF3<0> W83627HF/ F/ HG/ G TOVF3<8:1> Reserved ...
Page 73
... Bit 0： A one disables the corresponding interrupt status bit for SMI interrupt. 50h 00h Read Only 8 bits 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved 51h 00h Read/Write 8 bits 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved - 69 - W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 74
... Power on Default Value： Attribute： Size： Bit 7-0： Temperature 1 base temperature. The temperature is added by both monitor value and off- set value. 53h 00h Read/Write 8 bits EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved 54h 00h Read/Write 8 bits W83627HF/ F/ HG/ G OFFSET1<7:0> ...
Page 75
... Bit 7-0： Temperature 3 base temperature. The temperature is added by both monitor value and off- set value. Reserved Register - Index 57h ~ 58h These registers are reserved for Winbond internal use. 55h 00h Read/Write 8 bits 56h 00h Read/Write 8 bits W83627HF/ F/ HG/ G OFFSET2<7:0> OFFSET3<7:0> Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 76
... VCOREB is in the limit range. Bit 0： VCOREA Voltage Status. Set 1, the voltage of VCORE A is over the limit value. Set 0, the voltage of VCORE the limit range. 59h 00h Read Only 8 bits VCOREA_STS VCOREB_STS +3.3VIN_STS +5VIN_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS - 72 - W83627HF/ F/ HG/ G ...
Page 77
... Real Time Hardware Status Register III - Index 5Bh （Bank 4） Register Location： Power on Default Value： Attribute： Size： 5Ah 00h Read Only 8 bits +12VIN_STS -12VIN_STS -5VIN_STS FAN3_STS CASE_STS TEMP3_STS Reserved Reserved 5Bh 00h Read Only 8 bits - 73 - W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 78
... Bit 6-5： Reserved. Bit 4-0： Set 1, VID pins drive Set 0, VID pins drive a 0. Default 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved 5Dh <7：0> = 0000,0000h Read/Write 8 bits VIDOUT_0 VIDOUT_1 VIDOUT_2 VIDOUT_3 VIDOUT_4 Reserved Reserved VIDOUT_EN - 74 - W83627HF/ F/ HG/ G ...
Page 79
... AUTO-INCREMENT 50h 51h 52h 53h 54h 55h 56h 57h Winbond Test Register - Index 50h （Bank 6） This register is reserved for Winbond internal use. W83627HF/ F/ HG/ G BANK 5 （ ） DESCRIPTION 5VSB reading VBAT reading Reserved Reserved 5VSB High Limit 5VSB Low Limit. ...
Page 80
... SERIAL IRQ W83627HF supports a serial IRQ scheme. This allows a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame ...
Page 81
... Table 8-1 IRQSER Sampling periods SIGNAL SAMPLED IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned - 77 - W83627HF CLOCKS PAST START Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 82
... Plug and Play Configuration The W83627HF/F uses Compatible PNP protocol to access configuration registers for setting up dif- ferent types of configurations. In W83627HF/F, there are eleven Logical Devices（from Logical De- vice 0 to Logical Device B with the exception of logical device 4 for backward compatibility）which correspond to eleven individual functions： ...
Page 83
... Extended Functions Enable Registers （EFERs） After a power-on reset, the W83627HF/F enters the default operating mode. Before the W83627HF /Fenters the extended function mode, a specific value must be programmed into the Extended Func- tion Enable Register（EFER）so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers PC/AT system, their port addresses are 2Eh or 4Eh （ ...
Page 84
... Logical Device Number Reg. MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode | ;------------------------------------------ MOV DX,2EH MOV AL,AAH OUT DX,AL W83627HF ...
Page 85
... Power down 1： No Power down 4 URAPWD 0： Power down 1： No Power down 3 PRTPWD 0： Power down 1： No Power down Reserved. 0 FDCPWD 0： Power down 1： No Power down DESCRIPTION DEVICE REV DESCRIPTION - 81 - W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 86
... PNPCVS is 1. The corresponding power-on setting pin is NDTRA （pin 52）. CR25 （Default 0x00） BIT Reserved 5 URBTRI. UART2 output pin tri-stated. 4 URATRI. UART1 output pin tri-stated. 3 PRTTRI. Parallel port output pin tri-stated Reserved 0 FDCTRI. FDC output pin tri-stated. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION - 82 - ...
Page 87
... DSUBLGRQ 0： Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ 1： Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on se- lecting IRQ W83627HF/ F/ HG/ G DESCRIPTION Publication Release Date: June 09, 2006 - 83 - Revision 2.27 ...
Page 88
... SUSLED （SUSLED control bits are in CRF3 of Logical Device 9） 1： GP35 6 PIN69S 0： CIRRX# 1： GP34 5 PIN70S 0： RSMRST# 1： GP33 4 PIN71S 0： PWROK 1： GP32 3 PIN72S 0： PWRCTL# 1： GP31 2 PIN 73S 0： SLP_SX# 1： GP30 1 Reserved 0 Reserved W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION - 84 - ...
Page 89
... P16 1： GP14 1 PIN120S 0： MSO （MIDI Serial Output） 1： IRQIN0 （select IRQ resource through CRF4 Bit 7-4 of Logical Device 8） 1 PIN119S 0： MS1 （MIDI Serial Input） 1： GP20 W83627HF/ F/ HG/ G DESCRIPTION Publication Release Date: June 09, 2006 - 85 - Revision 2.27 ...
Page 90
... IRQIN1（select IRQ resource through CRF4 Bit 7-4 of Logical Device8） 11： GP27 CR2C （Default 0x00） Reserved CR2E （Default 0x00） Test Modes： Reserved for Winbond. CR2F （Default 0x00） Test Modes： Reserved for Winbond. W83627HF/ F/ HG/ G DESCRIPTION - 86 - ...
Page 91
... CR74 （Default 0x02 if PNPCVS = 0 during POR, default 0x04 otherwise） BIT Reserved These bits select DRQ resource for FDC. 000： DMA0 001： DMA1 010： DMA2 011： DMA3 100 ~ 111： No DMA active W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 87 - Revision 2.27 ...
Page 92
... Drive and Motor sel 0 and 1 are swapped Interface Mode 11： AT Mode （Default） 10： Reserved 01： PS/2 00： Model 30 1 FDC DMA Mode 0： Burst Mode is enabled 1： Non-Burst Mode （Default） 0 Floppy Mode 0： Normal Floppy Mode （Default） 1： Enhanced 3-mode FDD W83627HF/ F/ HG/ G DESCRIPTION - 88 - ...
Page 93
... Normal, use WP to determine whether the FDD is write protected or not. 1： FDD is always write-protected. CRF2 （Default 0xFF） BIT FDD D Drive Type FDD C Drive Type FDD B Drive Type FDD A Drive Type W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 89 - Revision 2.27 ...
Page 94
... DRATE0 MFM 1 1 1Meg 0 0 500K 0 1 300K 1 0 250K 1 1 1Meg 0 0 500K 0 1 500K 1 0 250K 1 1 1Meg 0 0 500K 0 1 2Meg 1 0 250K - 90 - W83627HF/ F/ HG/ G SELDEN FM --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 ...
Page 95
... DMA3 100 ~ 111： No DMA active TABLE B SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 DESCRIPTION DESCRIPTION DESCRIPTION - 91 - W83627HF/ F/ HG/ G DRIVE TYPE 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” （3-MODE） Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 96
... Mode （Default） 000：Standard and Bi-direction（SPP）mode 001：EPP - 1.9 and SPP mode 101：EPP - 1.7 and SPP mode 010：ECP mode 011：ECP and EPP - 1.9 mode 111：ECP and EPP - 1.7 mode W83627HF/ F/ HG/ G DESCRIPTION - 92 - ...
Page 97
... UART A clock source is 1.8462 Mhz （24MHz/13） 01： UART A clock source is 2 Mhz （24MHz/12） 10： UART A clock source is 24 Mhz （24MHz/1） 11： UART A clock source is 14.769 Mhz （24mhz/1.625） W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 93 - Revision 2 ...
Page 98
... RX mode to TX mode SUBCLKB1, SUBCLKB0 00： UART B clock source is 1.8462 Mhz （24MHz/13） 01： UART B clock source is 2 Mhz （24MHz/12） 10： UART B clock source is 24 Mhz （24MHz/1） 11： UART B clock source is 14.769 Mhz （24mhz/1.625） W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION - 94 - ...
Page 99
... SOUTB pin of UART B function or IRTX pin of IR function. 0 RX2INV. 0： the SINB pin of UART B function or IRRX pin of IR function in normal condition. 1： Inverse the SINB pin of UART B function or IRRX pin of IR function W83627HF/ F/ HG/ G DESCRIPTION IRTX tri-state Active pulse 1.6 μS ...
Page 100
... Select 12Mhz as KBC clock input. 11： Select 16Mhz as KBC clock input Reserved. 2 0： Port 92 disable. 1： Port 92 enable. 1 0： Gate20 software control. 1： Gate20 hardware speed up. 0 0： KBRST software control. 1： KBRST hardware speed up. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION - 96 - ...
Page 101
... These two registers select the Game Port base address [0x100：0xFFF byte boundary. CR62 （Default 0x03, 0x30 if PNPCVS = 0 during POR, default 0x00 otherwise） These two registers select the MIDI Port base address [0x100：0xFFF byte boundary. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION ...
Page 102
... If a port is programmed input port, then its respective bit can only be read. CRF2 （GP20-GP27 inversion register. Default 0x00） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION - 98 - ...
Page 103
... BIT 0x00 Time-out Disable 0x01 Time-out occurs after 1 sec / min 0x02 Time-out occurs after 2 sec / min 0x03 Time-out occurs after 3 sec / min . . . . 0xFF Time-out occurs after 255 sec / min W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 99 - Revision 2.27 ...
Page 104
... If a port is programmed input port, then its respective bit can only be read. CRF2 （GP30-GP35 inversion register. Default 0x00 Bit 7-6： Reserve） When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION - 100 - ...
Page 105
... Disable Mouse wake-up function. 1： Enable Mouse wake-up function. 4 MSRKEY. Select Mouse Left/Right Botton to wake-up system via PANSW_OUT. 0： Select click on Mouse Left-botton to wake the system up. 1： Select click on Mouse right-botton to wake the system up. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION DESCRIPTION PME . ...
Page 106
... CRE2 Keyboard Password Wake-Up Data Register This register holds the value of wake-up key register indicated by CRE1. W83627HF supports at most 5-key password wake-up function. CRE1 is an index register to indi- cate which byte of key code storage (0X00 ~ 0X0E) is going to be read or written. According to IBM 101/102 keyboard specification, a complete key code contains a 1-byte make code and a 2- byte break code. For example.The make code of Key “ ...
Page 107
... Password or Hot keys programmed in the registers. 1： Any key. Enable all wake-up event set in CRE0 can wake-up the system from S1/S2 state. This 2 bit is cleared when wake-up event occurs. 0： Disable. 1： Enable Reserved. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 103 - Revision 2.27 ...
Page 108
... Set this bit to “1” will make hardware monitor register index 42, bit 4 cleared unceas- ingly. Therefore, next Case-open Event can not be triggered again until this bit Is cleared to “0”. This bit is available for W83627HF A Version only, please refer to Hard- ware Monitor Register Index 46, bit 7 for other version. ...
Page 109
... Devices' trap status. 4 Reserved. Return zero when read Devices' trap status. W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 105 - Revision 2.27 ...
Page 110
... Enable the generation of an SMI / DESCRIPTION DESCRIPTION DESCRIPTION PME generation due to the device's IRQ. PME logic output =（MOUIRQEN and MOUIRQSTS）or（KBCIRQEN PME interrupt due to MOUSE's IRQ. PME interrupt due to MOUSE's IRQ. - 106 - W83627HF/ F/ HG/ G interrupt due to any IRQ of the de- ...
Page 111
... CIRIRQEN. 0： Disable the generation of an SMI / 1： Enable the generation of an SMI / 2 MIDIIRQEN. 0： Disable the generation of an SMI / 1： Enable the generation of an SMI / W83627HF/ F/ HG/ G DESCRIPTION PME interrupt due to KBC's IRQ. PME interrupt due to KBC's IRQ. PME interrupt due to printer port's IRQ. ...
Page 112
... Reserved. 0 Logic device activation control 1： Active 0： Inactived CR60 （Default 0x00, 0x00） These two registers select Hardware Monitor base address [0x100：0xFFF] on 8-byte boundary. W83627HF/ F/ HG/ G DESCRIPTION PME interrupt due to IRQIN1's IRQ. PME interrupt due to IRQIN1's IRQ. PME interrupt due to IRQIN0's IRQ. ...
Page 113
... These bits select IRQ resource for Hardware Monitor. CRF0 （Default 0x00） BIT Reserved. 0 Disable initial abnormal beep （VcoreA and +3.3 V） 0： Enable power-on abnormal beep 1： Disable power-on abnormal beep W83627HF/ F/ HG/ G DESCRIPTION DESCRIPTION Publication Release Date: June 09, 2006 - 109 - Revision 2.27 ...
Page 114
... SS MIN. TYP. MAX. I 2.4 BAT I 2.0 BAT +10 LIH I -10 LIL +10 LIH I -10 LIL - 110 - W83627HF/ F/ HG/ G UNIT V +0 ° C ° C UNIT CONDITIONS 2.5 V BAT 5.0 V, All ACPI SB pins are not connected μ μ - μA ...
Page 115
... LIH I -10 LIL +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH - 111 - W83627HF/ F/ HG/ G UNIT CONDITIONS - μ μ - μ 3.3V IN μ = - μ μ = - μ ...
Page 116
... V 0 +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0 +10 LIH I -10 LIL - 112 - W83627HF/ F/ HG/ G UNIT CONDITIONS μ =3. - μ 3.3V IN μ μ μ μ μ = μ μA ...
Page 117
... V 1.6 2.0 2 0 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL - 113 - W83627HF/ F/ HG/ G UNIT CONDITIONS = μ μ μ μ μ μ Publication Release Date: June 09, 2006 ...
Page 118
... Output pin with 16mA source-sink capability 16 Output Low Voltage Output High Voltage MIN. TYP. MAX. V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL 114 - W83627HF/ F/ HG/ G UNIT CONDITIONS μ μ μ μ - ...
Page 119
... Input Low Leakage MIN. TYP. MAX +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL - 115 - W83627HF/ F/ HG/ G UNIT CONDITIONS - μ μ μ 3.3V IN μ μ μ Publication Release Date: June 09, 2006 ...
Page 120
... V 0.5 1 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL - 116 - W83627HF/ F/ HG/ G UNIT CONDITIONS V V μ μ μ μ μ 3 μ μ μA ...
Page 121
... Voltage Hystersis Input High Leakage Input Low Leakage MIN. TYP. MAX. V 1.3 1 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL - 117 - W83627HF/ F/ HG/ G UNIT CONDITIONS μ μ μ μ Publication Release Date: June 09, 2006 Revision 2.27 ...
Page 122
... DCH2/PD4 18 RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram JP13 JP13 - 118 - W83627HF 13A DCH2 33 34 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 19 ...
Page 123
... Four FDD Mode W83627HF/ F/ HG/ G Publication Release Date: June 09, 2006 - 119 - Revision 2.27 ...
Page 124
... AM. MEGA. 87-96 821A2B282012345BC 1st line： Winbond logo 2nd line： the type number： W83627HF-AW, W83627F-AW, W83627HG-AW, W83627G-AW （the “G” means Pb-free package） 3rd line： the source of KBC F/W -- American Megatrends Incorporated 4th line： the tracking code 821 282012345BC 821： ...
Page 125
... QFP） 102 103 128 See Detail F y Seating Plane Detail F - 121 - W83627HF/ F/ HG/ G Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.10 0.20 0.30 0.004 0.008 c 0.20 ...
Page 126
... PD3 CAP NP 0.1u Printer PD0 PD1 PD[0..7] PD[0..7] PD2 PD3 PD4 PD5 PD6 PD7 ACK# BUSY PE SLCT VCC GND VCC3V GND Winbond Electronic Corp. Title W83627HF CIRCUIT (LPC I/O + H/W) Size Document Number B W83627HF + FDC Date: Monday, August 05, 2002 Sheet 1 Rev 0 ...
Page 127
... R26 OFF, D2,D3 ON: Wake_up fuction 0 R26 ON, D2,D3 OFF:NO Wake_up fuction D1 VCC IOVSB C14 5817 10u D2 5VSB 5817 WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/M) Size Document Number Custom KB & PS2 MOUSE & POWER Date: Monday, August 05, 2002 Publication Release Date: June 09, 2006 - 123 - ...
Page 128
... C24 C26 C28 C30 180 180 180 180 180 - 124 - VCC CIRRX 2 7 IOVSB CN2X5 DB25 WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/W) Size Document Number Custom COM & IR & LPT PORT Date: Monday, August 05, 2002 Sheet Rev 0.4 ...
Page 129
... C33 C32 C34 C35 C40 Publication Release Date: June 09, 2006 - 125 - WINBOND ELECTRONICS CORP. Title W83627HF CIRCUIT (LPC I/O + H/W) Size Document Number Rev Custom GAME & MIDI 0.4 Date: Monday, August 05, 2002 Sheet Revision 2.27 ...
Page 130
... R67 100 LS1 R66 10K SPEAKER Q3 BEEP 3904 Case Open Circuits R77 CASEOPEN# VBAT CASEOPEN SW L6 VCC AVCC FB L7 AGND FB Winbond Electronic Corp. Title W83627HF CIRCUIT (LPC I/O+ H/W) Size Document Number Custom Hardware Monitor Date: Monday, August 05, 2002 Sheet 5 Rev 0 ...
Page 131
... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83627HF/ F/ HG/ G Important Notice Publication Release Date: June 09, 2006 - 127 - ...