ISP1562BEGE ST-Ericsson Inc, ISP1562BEGE Datasheet - Page 49

• Manufacturer Part Number: ISP1562BEGE
• Description: IC USB PCI HOST CTRLR 100-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1562BEGE

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3157; ISP1562BE

NXP Semiconductors
Table 70.
Address: Content of the base address register + 34h
Table 71.
Address: Content of the base address register + 38h
[1]
ISP1562_2
Product data sheet
Bit
31
30 to 16 FSMPS
15 to 14 reserved -
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
Symbol
FIT
[14:0]
FI[13:0]
HcFmInterval - Host Controller Frame Interval register bit description
HcFmRemaining - Host Controller Frame Remaining register bit allocation
11.1.15 HcFmRemaining register
FRT
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
Frame Interval Toggle: The HCD toggles this bit whenever it loads a new value to Frame Interval.
FS Largest Data Packet: This field specifies the value that is loaded into the largest data packet
counter at the beginning of each frame. The counter value represents the largest amount of data in bits
that can be sent or received by the Host Controller in a single transaction at any given time, without
causing a scheduling overrun. The field value is calculated by the HCD.
Frame Interval: This specifies the interval between two consecutive SOFs in bit times. The nominal
value is set to 11,999. The HCD must store the current value of this field before resetting the Host
Controller to reset this field to its nominal value. The HCD can then restore the stored value on
completing the reset sequence.
reserved
This register is a 14-bit down counter showing the bit time remaining in the current frame.
Table 71
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
contains the bit allocation of this register.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 02 — 1 March 2007
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
FR[7:0]
reserved
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
FR[13:8]
[1]
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2007. All rights reserved.
ISP1562
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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