PDI1394L40BEGA ST-Ericsson Inc, PDI1394L40BEGA Datasheet - Page 10

• Manufacturer Part Number: PDI1394L40BEGA
• Description: IC IEEE 1394 LINK CTRLR 144-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394L40BEGA

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1176; PDI1394L40BE,551; PDI1394L40BE-S

Philips Semiconductors
9.3 AV Interface 2
NOTE: This AV interface may be configured to transmit or receive according to the condition of “DIRAV1” bit in GLOBCSR register—default is
receive.
2000 Dec 15
1394 enhanced AV link layer controller
142, 141, 140,
139, 136, 135,
134, 133
PIN No.
121
122
123
124
125
126
127
128
143
PIN SYMBOL
AV2ENDPCK
AV2READY
AV2FSYNC
AV2ERR0/
AV2ERR1/
AV2 D[7:0]
AV2VALID
AV2SYNC
LTLEND
AV2CLK
DATINV
AV2 SY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
CRC error, indicates bus packet containing AV2 D [7:0] had a CRC error, the current AV packet
is unreliable. This pin is also used to input the mode of LTLEND (Little Endian) bit after a chip
reset. An appropriate pull-up or pull-down resistor (22 k recommended) should be connected
to place the pin in the desired state during reset. Please see details related to use of the
LTLEND bit in the “Host Interface” section (of the datasheet (Section 12.5).
Sequence Error. Indicates at least one source packet was lost before the current AV2 D [7:0]
data. This pin is also used to input the mode of DATINV (Data Invariant) bit after a chip reset.
An appropriate pull-up or pull-down resistor (22 k recommended) should be connected to
place the pin in the desired state during reset. Please see details related to use of the DATINV
bit in the “Host Interface” section (of the datasheet (Section 12.5).
End of application packet indication from data source. Required only if input packet is not
multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size.
External application clock. Rising edge active. This pin can be programmed to be an output
and the application clock. Depending on the configuration of AV Port 2 as transmitter or
receiver, the output enable is located in the ITXPKCTL register (address 0x020) or IRXPKCTL
register (address 0x040).
Programmable frame sync, is set to input when AV interface 2 is a transmitter, and to output
when the interface is configures as a receiver. When the pin is an input, it is used to designate
a frame of data for Digital Video (DV). The signal is time stamped and transmitted in the SYT
field of ITXHQ2. When set to an output, the signal is derived from SYT field of IRXHQ2.
SY Value: When port AV2 is configured as a transmitter, this pin is an input. When the AV port
is configured to as a receiver, the pin is an output. See the description for bit 0 of the
ITXCTL (0x034) and IRXCTL (0x054) registers.
Indicates data on AV2 D [7:0] is valid.
Indicates that the data currently being clocked by the source under the condition of AV2VALID
is the start of an application packet. If the AV interface is configured as a receiver, then it will
assert AV2SYNC when an application packet becomes available and persist until the first data
of the packet is clocked out. Thus, AV2VALID may last for more than one cycle, but for exactly
one cycle in which AV2VALID is asserted.
Audio/Video Data 7 (MSB) through 0. Part of byte-wide interface to the AV layer 2.
When the AV port is configured as a receiver, this pin is an input. This is a flow control signal
that allows the application to indicate whether it is able to accept data flowing across
AV Interface 2. The AV interface responds to an inactive AV2READY by not asserting
AV2VALID, and thereby withholding data from the application.
The AV2READY signal is processed through one level of pipelining, which means that the
AV Link will accept data on the cycle in which AV2READY is de-asserted and will not accept
data on the cycle in which AV2READY is asserted.
When the AV port is configured to transmit, this pin is an output. This is a flow control signal
that allows the link chip to indicate whether it is able to accept data flowing across
AV Interface 2. The source of data, and external entity, responds to an inactive AV2READY by
not asserting AV2VALID, and thereby withholding data.
The AV2READY signal should be processed by the sink through one level of pipelining, which
means that the receiver must be able to accept data on the cycle in which AV2READY is
de-asserted. The receiving interface does not have to accept data on the cycle in which
AV2READY is asserted.
6
NAME AND FUNCTION
PDI1394L40
Preliminary specification