AD7869JN Analog Devices Inc, AD7869JN Datasheet - Page 2

• Manufacturer Part Number: AD7869JN
• Description: IC I/O PORT 14BIT ANLG 24-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7869JN

• Rohs Status: RoHS non-compliant
• Applications: Analog I/O
• Interface: TTL/CMOS
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 24-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Converter Type: ADC/DAC
• Resolution: 14b
• Number Of Dac's: Single
• Data Rate: 0.083MSPS
• Digital Interface Type: Serial
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

ADC SECTION
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
REFERENCE OUTPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION TIME
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
7
8
Specifications subject to change without notice.
AD7869–SPECIFICATIONS
Temperature ranges are as follows: J Version, 0 C to +70 C; A Version, –40 C to +85 C.
V
SNR calculation includes distortion and noise components.
SNR degradation due to asynchronous DAC updating during conversion is 0.1 dB typ.
Measured with respect to internal reference.
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
Tying the CONTROL input to V
Sample tested @ +25 C to ensure compliance.
IN
Signal-to-Noise Ratio
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Track/Hold Acquisition Time
Resolution
Minimum Resolution
Integral Nonlinearity
Differential Nonlinearity
Bipolar Zero Error
Positive Gain Error
Negative Gain Error
Input Voltage Range
Input Current
RO ADC @ +25 C
RO ADC TC
Reference Load Sensitivity
(CONVST, CLK, CONTROL)
DR, RFS Outputs
RCLK Output
DR, RFS, RCLK Outputs
External Clock
Internal Clock
V
V
I
I
Total Power Dissipation
DD
SS
DD
SS
= 3 V.
T
Second Order Terms
Third Order Terms
( RO ADC vs. I)
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Current
Input Capacitance, C
Output Low Voltage, V
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
MIN
to T
MAX
7
(CONTROL & CLK)
IN
5
5
3, 4
(V
All specifications T
6
IN
DD
INL
(SNR) @ +25 C
INH
8
OL
OL
= +5 V
DD
2
places the device in a factory test mode where normal operation is not exhibited.
5%, V
8
MIN
SS
to T
J Version
78
78
–86
–86
–86
–88
2
14
14
2.99/3.01
–1.5
2.4
0.8
10
0.4
0.4
15
10
10
+5
–5
22
12
170
= –5 V
2
1
20
20
20
3
1
25
10
10
10
MAX
unless otherwise noted.)
1
5%, AGND = DGND = 0 V, f
–86
–86
–86
–88
14
14
2.4
0.8
0.4
0.4
10
10
170
A Version
78
77
2
2.99/3.01
–1.5
10
15
+5
–5
22
12
2
1
20
20
20
3
1
25
40
10
10
10
–2–
1
Units
dB min
dB min
dB typ
dB typ
dB typ
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
Volts
mA max
V min/ V max
ppm/ C typ
mV max
V min
V max
pF max
V max
V max
pF max
V nom
V nom
mA max
mA max
mW max
s max
A max
A max
A max
s max
s max
ppm/ C max
CLK
= 2.0 MHz external.
Test Conditions/Comments
V
V
V
fa = 9 kHz, fb = 9.5 kHz, f
fa = 9 kHz, fb = 9.5 kHz, f
No Missing Codes Are Guaranteed
Reference Load Current Change (0–500 A),
Reference Load Should Not Be Changed
During Conversion
V
V
V
V
I
I
The Internal Clock Has a Nominal Value of 2.0 MHz
For Both DAC and ADC
Cumulative Current from the Two V
Cumulative Current from the Two V
Typically 130 mW
SINK
SINK
IN
IN
IN
DD
DD
IN
IN
5% for Specified Performance
5% for Specified Performance
= 10 kHz Sine Wave, f
= 10 kHz Sine Wave, f
= 10 kHz Sine Wave, f
= 0 V to V
= V
= 5 V
= 5 V
= 1.6 mA, Pull-Up Resistor = 4.7 k
= 2.6 mA, Pull-Up Resistor = 2 k
SS
to DGND
5%
5%
DD
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
= 83 kHz
= 83 kHz
= 83 kHz
= 50 kHz
= 50 kHz
DD
SS
Pins
Pins
REV. A