MT18HTF25672PKZ-80EH1 Micron Technology Inc, MT18HTF25672PKZ-80EH1 Datasheet - Page 10
MT18HTF25672PKZ-80EH1
Manufacturer Part Number
MT18HTF25672PKZ-80EH1
Description
MODULE DDR2 SDRAM 2GB 244MRDIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet
1.MT18HTF25672PKZ-80EH1.pdf
(15 pages)
Specifications of MT18HTF25672PKZ-80EH1
Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
800MT/s
Features
-
Package / Case
244-MiniRDIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
I
Table 8:
PDF: 09005aef83d235f2/Source: 09005aef83d23625
htf18c256x72pkz.fm - Rev. A 11/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads,
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
t
valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are
switching
DD
OUT
OUT
RAS =
RCD =
CK =
RP =
RC =
DD
),
Specifications
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
t
RP (I
RP =
RC (I
CK (I
t
t
RAS MIN (I
RCD (I
DD
DD
DD
DD
t
), AL = 0;
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb
(128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus inputs
DD
t
RRD =
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus
t
Notes: 1. Value calculated as one module rank in this operating condition, all other module ranks in
CK =
DD
t
RRD (I
t
CK =
Specifications and Conditions – 2GB
t
CK (I
t
DD
DD
CK =
2. Value calculated reflects all module ranks in this operating condition.
DD
t
CK (I
), AL = 0;
), AL =
),
I
DD
DD2P
t
t
RCD =
),
CK (I
DD
t
RC =
(CKE LOW) mode.
); REFRESH command at every
t
RCD (I
DD
t
t
CK =
RCD (I
),
t
RC (I
t
RAS =
DD
DD4W
t
CK (I
) -1 x
DD
DD
t
),
CK =
); CKE is HIGH, S# is HIGH between
t
t
RAS MAX (I
t
DD
CK =
t
RAS =
CK =
t
CK (I
),
t
CK (I
t
RAS =
t
t
OUT
CK (I
CK =
t
DD
CK (I
t
t
CK =
10
RAS MIN (I
DD
);
= 0mA; BL = 4,
DD
t
DD
t
DD
),
t
CK =
CK (I
RAS MAX (I
t
),
2GB (x72, DR) 244-Pin DDR2 Mini-RDIMM
CK (I
t
),
); CKE is HIGH, S# is
RAS =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
RC =
RP =
t
DD
t
RFC (I
CK (I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
); CKE is LOW;
t
); CKE is
t
),
RAS MAX
t
RC (I
RP (I
DD
DD
DD
),
)
DD
),
DD
),
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
1
1
2
2
1
2
2
1
2
2
2
1
©2009 Micron Technology, Inc. All rights reserved.
I
DD
-80E
-800
1053
1080
1503
1503
4230
3078
873
126
900
900
720
180
126
Specifications
-667
1278
1278
3870
2583
828
963
126
720
720
540
180
990
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA