DS33M31N+ Maxim Integrated Products, DS33M31N+ Datasheet - Page 13

• Manufacturer Part Number: DS33M31N+
• Description: IC MAPPER ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33M31N+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.4.1.4 Trace Identifier Controller
1.4.1.5 Bit Error Rate Tester (BERT)
1.4.2 DS3/E3 Ethernet Mapping (DS33M31 and DS33M33 only)
1.4.3 Line DS3/E3 Framer/Formatter (DS33M33 only)
1.4.3.1 Line DS3/E3 Framer
Rev: 111908
___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET
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Three trace identifier controllers per port for
A trace identifier controller for each optional VC-4 path trace (J1)
Software programmable trace identifier mode: 16-byte trail trace access point or 64-byte path trace
Extraction and storage of the incoming trace identifier message in a 64/16-byte receive register
Software programmable incoming expected trace identifier message
Software programmable outgoing trace identifier message or idle trace identifier message
Incoming trace identifier mismatch, unstable, idle, and change indications
Insertion of the outgoing trace identifier message from a 64/16-byte transmit register
One BERT per port software programmable for insertion
Generates and detects pseudo-random patterns of length 2n – 1 (n = 1 to 32) and repetitive patterns from
1 to 32 bits in length
Supports pattern insertion/extraction in DS3/E3 payload, or entire data stream
Supports pattern insertion/extraction in STS-1/VC-3/VC-4 payload, or entire STS-1 SPE/AU-3/AU-4
Large 24-bit error and 32-bit bit counters allow testing over long periods without host intervention
Errors can be inserted in BERT patterns for diagnostic purposes (single bit errors or specific bit-error rates)
Pattern synchronization even in the presence of 10-3 bit error rate
Mapping/Demapping of encapsulated Ethernet packets into/out-of the payload of the Add/Drop DS3/E3.
Frame synchronization for M23 DS3, C-bit Parity DS3, G.751 E3, and G.832 E3
Detection of DS3 loss of signal (LOS), loss of frame (LOF), out of frame (OOF), out of multiframe (OOMF),
severely error frame (SEF), change of frame alignment (COFA), remote defect indication (RDI), alarm
indication signal (AIS), receive unframed all ones, idle signal, DS3 application ID bit, and DS3 format
mismatch
Detection of G.751 E3 LOS, LOF, OOF, COFA, remote alarm indication (RAI), and AIS
Detection of G.832 E3 LOS, LOF, OOF, COFA, RDI, and AIS
Detection and accumulation of F-bit errors, M-bit errors, FAS errors, FA1 and FA2 byte errors, OOF
occurrences, P-bit parity errors, C-bit parity errors, BIP-8 (bit or block basis) errors, far end block errors
(FEBE), and remote error indications (REI)
Fully programmable automatic AIS insertion upon detection of LOS, OOF, and/or AIS
All DS3/E3 overhead fields are presented on the associated receive DS3/E3 overhead output port
Extraction of HDLC data stream from DS3 path maintenance data link (PMDL), G.751 E3 national bit, or
G.832 E3 NR or GC bytes
Extraction of FEAC data from DS3 FEAC bit or G.751 E3 alarm bit
Extraction of trail trace access point identifier from G.832 E3 TR byte
Framer pass-through mode for clear channel applications and externally defined frame formats
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the line/tributary side G.832 trail trace (TR),
the system/trunk side G.832 trail trace (TR), and system/trunk side STS-1/VC-3 path trace (J1) in
DS3/E3 mode, or
the STS-1 section trace (J0), line/tributary side STS-1 path trace (J1), and system/trunk side STS-
1/VC-3 path trace (J1) in STS-1 mode.
Into DS3/E3 payload toward DS3/E3 Line interface, or
Into DS3/E3 payload mapped to STS-1 toward STS-3/STM-1 interface, or
Into STS-1 payload toward STS-3/STM-1 interface
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