MT16HTF12864HZ-667G1 Micron Technology Inc, MT16HTF12864HZ-667G1 Datasheet - Page 11
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MT16HTF12864HZ-667G1
Manufacturer Part Number
MT16HTF12864HZ-667G1
Description
MODULE DDR2 SDRAM 1GB 200SODIMM
Manufacturer
Micron Technology Inc
Series
-r
Datasheet
1.MT16HTF12864HZ-667G1.pdf
(18 pages)
Specifications of MT16HTF12864HZ-667G1
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
667MT/s
Features
-
Package / Case
200-SODIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
IDD Specifications
Table 10: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
PDF: 09005aef8339ef97
htf16c128_256_512x64hz.pdf - Rev. C 9/10 EN
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
ing; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
RAS =
CK =
OUT
DD
DD
t
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
),
DD
= 0mA; BL = 4, CL = CL (I
t
t
RP =
CK (I
), AL = 0;
DD
t
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
DD
t
RP (I
); CKE is LOW; Other control and address
t
DD
DD
CK =
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
CK (I
Specifications and Conditions – 1GB
t
CK =
DD
t
DD
CK =
),
t
CK (I
), AL = 0;
t
RC =
t
CK (I
DD
DD4W
t
); REFRESH command at every
RC (I
DD
t
1GB, 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM
CK =
),
DD
t
RAS =
),
t
t
CK (I
RAS =
t
CK =
t
t
RAS MAX (I
CK =
DD
t
CK =
t
),
RAS MIN (I
t
t
CK (I
Fast PDN exit MR[12] = 0
Slow PDN exit MR[12] = 1
RAS =
t
CK (I
t
OUT
CK =
t
t
CK (I
CK =
11
DD
= 0mA; BL = 4, CL =
DD
DD
t
),
t
DD
RAS MAX (I
CK (I
),
t
DD
),
t
CK (I
); CKE is HIGH,
RAS =
t
RC =
t
),
RP =
t
RFC (I
DD
t
RCD =
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
t
); CKE is
t
RC (I
RAS MAX
RP (I
DD
DD
) inter-
t
RCD
DD
),
DD
t
),
RP
);
Symbol -1GA
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
© 2008 Micron Technology, Inc. All rights reserved.
IDD Specifications
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
-80E/
1120 1040
1616 1416
1696 1496
3680 2880
-800
856
979
112
800
880
640
192
112
-667 Units
776
896
112
720
800
560
192
112
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA