SEG02G72B1BH2MT-30R Swissbit NA Inc, SEG02G72B1BH2MT-30R Datasheet

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SEG02G72B1BH2MT-30R

Manufacturer Part Number
SEG02G72B1BH2MT-30R
Description
DRAM DDR2 2GB 200-SORDIMM W/ECC
Manufacturer
Swissbit NA Inc
Series
-r
Datasheet

Specifications of SEG02G72B1BH2MT-30R

Memory Type
DDR2 SDRAM
Memory Size
2GB
Speed
667MHz
Features
-
Package / Case
200-SORDIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1052-1044
2GB DDR2
200 Pin So-RDIMM
SEG02G72B1BH2MT-xxR
2GByte in FBGA Technology
RoHS compliant
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
Options:
Environmental Requirements:
* The refresh rate has to be doubled when 85°C>T
Data Rate / Latency
DDR2 667 MT/s CL5
DDR2 533 MT/s CL4
Standard Grade
Grade W
Operating temperature (T
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Module densities
2GB with 18 dies and 2 rank
Standard Grade
Grade W
(T
(T
(T
(T
C
)
A
C
A
C
)
)
)
)
– SDRAM registered So-RDIMM
1
0°C to 85°C
-40°C to 95°C*
the reference according MO224
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
-40°C to 95°C*
-40°C to 85°C
0°C to 70°C
0°C to 85°C
Marking
C
>95°C
-30
-37
Data Sheet
Features:
Figure: mechanical dimensions
200-pin 72-bit Small Outline Registered Dual-In-Line
Double Data Rate Synchronous DRAM Module
Module organization: dual rank 256Mx72
V
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Phase-lock loop (PLL) clock driver to reduce loading
Supports ECC error detection and correction
Gold-contact pad
This module family is fully pin and functional
compatible to the JEDEC PC2-5300 spec. and
JEDEC- Standard MO 224. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR2 - SDRAM component base Micron
MT47H128M8 DIE Rev. H
128Mx8 DDR2 SDRAM in FBGA-60 package
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent operation
WRITE latency = READ latency – 1 t
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
DD
= 1.8V +0.1V, V
www.swissbit.com
eMail: info@swissbit.com
DDQ
= 1.8V +0.1V
Rev.1.0
CK
30.07.2010
Page 1
of 14

Related parts for SEG02G72B1BH2MT-30R

SEG02G72B1BH2MT-30R Summary of contents

Page 1

... DDR2 – SDRAM registered So-RDIMM 200 Pin So-RDIMM SEG02G72B1BH2MT-xxR 2GByte in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 667 MT/s CL5 DDR2 533 MT/s CL4  Module densities 2GB with 18 dies and 2 rank  Standard Grade (  Grade W ...

Page 2

... The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used 256M x 72bit 18 x 128M x 8bit (1024Mbit) Timing Parameters Part Number SEG02G72B1BH2MT-30[W]R SEG02G72B1BH2MT-37[W]R Pin Name A0 - A13 BA0 – BA2 DQ0 – DQ63 DM0-DM8 RAS# CAS# WE# ...

Page 3

REF DDSPD SCL SDA SA0 – SA1 ODT0 / ODT1 NC Pin Configuration PIN # Front Side PIN # 1 V REF 3 DQ0 DQ1 9 DQS0# 11 DQS0 13 ...

Page 4

PIN # Front Side PIN # 65 DQS3 DQ26 71 DQ27 CB0 77 CB1 DQS8# 83 DQS8 CKE0 89 CKE1 91 NC (S2#) 93 ...

Page 5

FUNCTIONAL BLOCK DIAGRAMM 2GB DDR2 ECC Registered SoDIMM, 2 RANKS AND 18 COMPONENTS Swissbit Industriestrasse 4 CH-9552 Bronschhofen Switzerland Data Sheet www.swissbit.com Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com Rev.1.0 30.07.2010 ...

Page 6

... When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. ...

Page 7

I Specifications and Conditions DD (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DDQ Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge ...

Page 8

Parameter & Test Condition OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active MAX ( RAS ...

Page 9

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DDQ AC CHARACTERISTICS PARAMETER SYMBOL Clock cycle time ...

Page 10

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DD AC CHARACTERISTICS PARAMETER SYMBOL Address and control input hold t IH time CAS# to ...

Page 11

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ T ≤ + 85° +1.8V ± 0.1V, V CASE DD AC CHARACTERISTICS PARAMETER SYMBOL ODT power-down exit latency t AXPD ODT enable from MRS ...

Page 12

SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION 0 NUMBER OF SPD BYTES USED 1 TOTAL NUMBER OF BYTES IN SPD DEVICE 2 FUNDAMENTAL MEMORY TYPE 3 NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON 4 ASSEMBLY 5 DIMM HIGHT ...

Page 13

... *RoHs compl. DDR2-667MT/s Chip Vendor (MICRON) 2 Module Rank Chip Rev. H Page ...

Page 14

Locations Swissbit Industriestrasse 4 CH-9552 Bronschhofen Switzerland Data Sheet Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D – 12681 ...

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