MC10EP446FAG ON Semiconductor, MC10EP446FAG Datasheet - Page 14

• Manufacturer Part Number: MC10EP446FAG
• Description: IC CONV 8BIT SER/PAR ECL 32LQFP
• Manufacturer: ON Semiconductor

Specifications of MC10EP446FAG

• Interface: Differential
• Voltage - Supply: 3 V ~ 5.5 V
• Package / Case: 32-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: MC10EP446FAGOS

clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the
parallel input data after the a falling edge of SYNC ¬, followed by the falling edge CLK ­, on the next rising of edge of CLK
® for CKSEL LOW
CKSEL
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
SYNC
SOUT
(Asynchronous RESET)
PCLK
CLK
D0
D1
D2
D3
D4
D5
D6
D7
SYNC
(Synchronous ENABLE)
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
SYNC
Data Latched
À
Á
Number of Clock Cycles from Data Latch to SOUT
Â
Figure 10. Synchronous Release of SYNC for CKSEL LOW
D1−1
D0−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
1
SYNC
2
CLK
3
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Data Latched
4
14
À
D1−2
D0−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
5
Á
6
Â
7
Data Latched
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
Data Latched
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4