BD8964FVM-TR Rohm Semiconductor, BD8964FVM-TR Datasheet - Page 10
![no-image](/images/manufacturer_photos/0/5/572/rohm_semiconductor_sml.jpg)
BD8964FVM-TR
Manufacturer Part Number
BD8964FVM-TR
Description
IC SWITCHING REG W/MOSFET MSOP8
Manufacturer
Rohm Semiconductor
Series
-r
Type
Step-Down (Buck), PWM - Current Moder
Datasheet
1.BD8964FVM-TR.pdf
(14 pages)
Specifications of BD8964FVM-TR
Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
1 V ~ 1.8 V
Current - Output
1.2A
Frequency - Switching
1MHz
Voltage - Input
4 V ~ 5.5 V
Operating Temperature
-25°C ~ 85°C
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
© 2009 ROHM Co., Ltd. All rights reserved.
BD8964FVM
www.rohm.com
4. Determination of RITH, CITH that works as a phase compensator
5. Determination of output voltage
V
CC
Phase
Phase
[deg]
[deg]
Gain
Gain
[dB]
[dB]
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
The output voltage V
V
With R1 and R2 adjusted, the output voltage may be determined as required.
Use 1 kΩ~100 kΩ resistor for R1. If a resistor of the resistance higher than
100 kΩ is used, check the assembled set carefully for ripple voltage etc.
(Adjustable output voltage range: 1.0V~1.8V)
OUT
-90
-90
A
A
0
0
0
0
=(R2/R1+1)×V
fz
Fig.29 Error amp phase compensation characteristics
(Amp.)
V
R
C
OUT
Cin
Fig.28 Open loop gain characteristics
ITH
ITH
= fp
2π×R
Fig.30 Typical application
I
(Min.)
OUT
fp(Min.)
fz(Amp.)
Min.
EN
V
ITH
ITH
OUT
OUT
ADJ
1
×C
・・・(7) V
fp(Max.)
is determined by the equation (7):
ITH
V
GND,PGND
I
CC
OUT
,PV
Max.
CC
=
ADJ
SW
fz(ESR)
2π×R
: Voltage at ADJ terminal (0.8V Typ.)
OMax.
L
ESR
C
1
O
×C
O
10/13
fp=
fz
Pole at power amplifier
Zero at power amplifier
(ESR)
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
R
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
O
2π×R
=
V
OUT
2π×E
1
O
×C
fp
fp
fz
1
SR
O
(Amp.)
(Min.)
(Max.)
×C
=
O
=
=
Fig.31 Determination of output voltage
2π×R
2π×R
2π×R
1
6
OMax.
OMin.
ITH
SW
ADJ
1
1
1
×C
×C
×C
ITH
O
O
4.7µH
[Hz]←with lighter load
[Hz] ←with heavier load
10µF
Technical Note
2009.05 - Rev.A
R2
R1
Output