MT41J128M16HA-125G:D Micron Technology Inc, MT41J128M16HA-125G:D Datasheet - Page 20
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT41J128M16HA-125G:D
Manufacturer Part Number
MT41J128M16HA-125G:D
Description
IC DDR3 SDRAM 2GBIT 96FBGA
Manufacturer
Micron Technology Inc
Series
-r
Datasheet
1.MT41J256M8JE-187EA.pdf
(181 pages)
Specifications of MT41J128M16HA-125G:D
Format - Memory
RAM
Memory Type
DDR3 SDRAM
Memory Size
2G (128M x 16)
Speed
800MHz
Interface
Parallel
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 95°C
Package / Case
96-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT41J128M16HA-125G:D
Manufacturer:
MICRON
Quantity:
2 890
Company:
Part Number:
MT41J128M16HA-125G:D
Manufacturer:
Micron
Quantity:
9
Company:
Part Number:
MT41J128M16HA-125G:D
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT41J128M16HA-125G:D
Manufacturer:
MICRON/美光
Quantity:
20 000
Company:
Part Number:
MT41J128M16HA-125G:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 4:
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D2.fm - Rev G 2/09 EN
L9, L3, M9, M3,
K4, L8, L4, K3,
Ball Number
N9, M4, H8,
F4, G4, H4
J3, K9, J4
M8, K8,
N4, N8
F8, G8
G10
H3
G2
B8
82-Ball FBGA (x4, x8)
RAS#, CAS#, WE#
A8, A9, A10/AP,
A0, A1, A2, A3
A4, A5, A6, A7
BA0, BA1, BA2
A11, A12/BC#
A13, A14
Symbol
CK, CK#
ODT
CKE
CS#
DM
Input
Input
Input
Input
Input
Input
Input
Input
Type
Description
Address inputs: Provide the row address for ACTIVATE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in
the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs
also provide the op-code during a LOAD MODE command. Address
inputs are referenced to V
mode register (MR), A12 is sampled during READ and WRITE
commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See
Table 65 on page 93.
Bank address inputs: BA[2:0] define the bank to which an
ACTIVATE, READ, WRITE, or PRECHARGE command is being applied.
BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is
loaded during the LOAD MODE command. BA[2:0] are referenced to
V
Clock: CK and CK# are differential clock inputs. All control and
address input signals are sampled on the crossing of the positive
edge of CK and the negative edge of CK#. Output data strobe (DQS,
DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables
(registered LOW) internal circuitry and clocks on the DRAM. The
specific circuitry that is enabled/disabled is dependent upon the
DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry and exit and for self refresh
entry. CKE is asynchronous for self refresh exit. Input buffers
(excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
power-down. Input buffers (excluding CKE and RESET#) are disabled
during SELF REFRESH. CKE is referenced to V
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external rank selection on systems
with multiple ranks. CS# is considered part of the command code.
CS# is referenced to V
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with the input data
during a write access. Although the DM ball is input-only, the DM
loading is designed to match that of the DQ and DQS balls. DM is
referenced to V
On-die termination: ODT enables (registered HIGH) and disables
(registered LOW) termination resistance internal to the DDR3
SDRAM. When enabled in normal operation, ODT is only applied to
each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8;
DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if
disabled via the LOAD MODE command. ODT is referenced to
V
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered and are referenced to V
REF
REF
CA.
CA.
20
REF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ. DM has an optional use as TDQS on the x8.
Ball Assignments and Descriptions
REF
CA.
REF
2Gb: x4, x8, x16 DDR3 SDRAM
CA. A12/BC#: When enabled in the
©2006 Micron Technology, Inc. All rights reserved.
REF
CA.
REF
CA.