MT41K512M4HX-15E:D Micron Technology Inc, MT41K512M4HX-15E:D Datasheet
MT41K512M4HX-15E:D
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MT41K512M4HX-15E:D Summary of contents
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DDR3L SDRAM Addendum MT41K512M4 – 64 Meg banks MT41K256M8 – 32 Meg banks MT41K128M16 – 16 Meg banks Description DDR3L SDRAM (1.35V low voltage version ...
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Table 2: Addressing Parameter Configuration Refresh count Row address Bank address Column address PDF: 09005aef83ed2952 2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN 2Gb: x4, x8, x16 DDR3L SDRAM Addendum 512 Meg Meg banks 32 ...
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Ball Assignments and Descriptions Figure 1: 78-Ball FBGA – x4, x8 Ball Assignments (Top View Ball descriptions listed in Table 3 (page 5) are listed as ...
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Figure 2: 96-Ball FBGA – x16 Ball Assignments (Top View Ball descriptions listed in Table 4 (page 7) are listed as “x16.” Notes: ...
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... READ/WRITE commands, to select one location A[14:13] out of the memory array in the respective bank. A10 sampled during a PRECHARGE com- mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command ...
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Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type Description DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are refer- enced to V DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned ...
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... A11, A12/BC#, A13 address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE com- mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command ...
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Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with the ...
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Package Dimensions Figure 3: 78-Ball FBGA – x4, x8 (DA) Seating Plane A 0.12 A 78X Ø0.45 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post-reflow Ø0.35 SMD ball ...
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Figure 4: 78-Ball FBGA – x4, x8; Die Rev. D (HX) 0.155 78X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 11.5 ±0.1 9.6 CTR 0.8 TYP 1. All dimensions are in millimeters. Notes: 2. Solder ...
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Figure 5: 96-Ball FBGA – x16; Die Rev. D (HA) Seating plane A 0.12 A 96X Ø0.45 Solder ball material: SAC305. Dimensions apply to solder balls post-reflow Ø0.35 SMD ball pads. 12 CTR 0.8 TYP 0.8 ...
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Electrical Characteristics – I Table 5: I Maximum Limits – Rev Speed Bin I Width DD I x4, 8 DD0 x16 I x4, 8 DD1 x16 I All DD2P0 I x4, 8 DD2P1 x16 I All DD2Q I ...
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Table 6: I Maximum Limits – Die Rev H DD Speed Bin I Width DD I x4, 8 DD0 I x4, 8 DD1 I (Slow) x4, 8 DD2P0 I (Fast) x4, 8 DD2P1 I x4, 8 DD2Q I x4, 8 ...
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Table 7: I Maximum Limits – Die Rev M DD Speed Bin I Width DD I x4, 8 DD0 I x4, 8 DD1 I (Slow) x4, 8 DD2P0 I (Fast) x4, 8 DD2P1 I x4, 8 DD2Q I x4, 8 ...
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Electrical Specifications Table 8: Input/Output Capacitance Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Capacitance Parame- ters Symbol Single-end I/O: DQ Differential I/O: DQS DQS#, TDQS, TDQS# Inputs (CTRL, ...
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Table 11: Input Switching Conditions – Command and Address (Continued) Parameter/Condition Input low DC voltage: Logic 0 Table 12: Input Switching Conditions – DQ and DM Parameter/Condition Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input ...
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Table 15: R Effective Impedance TT Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet MR1 [ Resistor TT 120Ω TT,120PD240 R TT,120PU240 120Ω 60Ω ...
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Table 16: Reference Settings for ODT Timing Measurements Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Measured Parameter R TT,nom t AON AOF AONPD ...
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Table 19: Single-Ended Output Driver Characteristics Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet Parameter/Condition Output slew rate: Single-ended; For rising and falling edges, measure between OL(AC) and ...
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Table 22: Derating Values for CMD/ADDR 4.0 V/ns 3.0 V/ns Slew Rate Δ t Δ t Δ 0.9 –1 –3 –1 0.8 –3 ...
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Table 24: Required Time VAC Above V ued) Slew Rate (V/ns) 0.7 0.6 0.5 <0.5 Table 25: Derating Values for 4.0 V/ns 3.0 V/ns DQ Slew Δ DS Δ DH Δ DS Δ Rate V/ns 2.0 ...
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Table 27: Required Time VAC Above V Slew Rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 <0.5 Initialization If the SDRAM is powered up and initialized for the 1.35V operating voltage range, volt- age can be ...
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V Voltage Switching DD After the DDR3L DRAM is powered up and initialized, the power supply can be altered between the DDR3L and DDR3 levels, provided the sequence in Figure 6 is maintained. Figure 6: V Voltage Switching DD Tb ...