AT24C128C-SSHM-B Atmel, AT24C128C-SSHM-B Datasheet - Page 8

• Manufacturer Part Number: AT24C128C-SSHM-B
• Manufacturer: Atmel

Specifications of AT24C128C-SSHM-B

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.
6.
8
Figure 4-6.
Device Addressing
The 128K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write
operation (see
significant bits, as shown. This is common to all two-wire EEPROM devices.
Figure 5-1.
The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same bus. These
bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit
that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to
a standby state.
DATA SECURITY: The Atmel AT24C128C has a hardware data protection scheme that allows the user to write protect the
whole memory when the WP pin is at V
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero, and then clock in the first 8-bit
data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a
microcontroller, must then terminate the write sequence with a stop condition. At this time, the EEPROM enters an
internally-timed write cycle, t
EEPROM will not respond until the write is complete (see
Atmel AT24C128C
MSB
DATA OUT
DATA IN
1
SCL
Output Acknowledge
Device Address
0
Figure
START
5-1). The device address word consists of a mandatory one-zero sequence for the first four most-
1
WR
1
, to the nonvolatile memory. All inputs are disabled during this write cycle, and the
0
CC
.
A2
A1
8
Figure
A0
ACKNOWLEDGE
6-1).
9
LSB
R/W
8734A–SEEPR–1/11