MCZ33989EGR2 Freescale Semiconductor, MCZ33989EGR2 Datasheet - Page 26

• Manufacturer Part Number: MCZ33989EGR2
• Description: IC SYSTEM BASIS CHIP CAN 28-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33989EGR2

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 28-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE POWER-UP, SBC WAKE-UP
up from Sleep mode, it enters into Reset mode prior to
moving into Normal Request mode.
DEBUG MODE: HARDWARE AND SOFTWARE
DEBUG WITH THE SBC
board as the microcontroller it supplies, both application
software and SBC dedicated routine must be debugged. The
following features allow debug of the software by allowing the
possibility of disabling the SBC internal software Watchdog
timer.
DEVICE POWER-UP, RESET PIN CONNECTED TO
VDD1
SPI communication occurs to configure the device, a reset
occurs every 350 ms. In order to allow software debug and
avoid MCU reset, the Reset pin can be connected directly to
VDD1 by a jumper.
DEBUG MODES WITH SOFTWARE WATCHDOG
DISABLED THOUGH SPI (NORMAL DEBUG,
STANDBY AND STOP DEBUG)
avoid unwanted watchdog disable while limiting the risk of
disabling Watchdog during SBC normal operation, the
watchdog disable must be achieved the following sequence:
• Step 1–Power down the SBC
MCU FLASH PROGRAMMING CONFIGURATION
EEPROM or Flash) the SBC capabilities allows the V
be forced by an external power supply to 5.0 V; the reset and
WD outputs by external signal sources are forced to zero or
5.0 V, both without damage. This allows, for example, supply
of the complete application board by external power supply,
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33989
FUNCTIONAL DEVICE OPERATION
RESET AND WATCHDOG PINS, SOFTWARE WATCHDOG OPERATIONS
After device or system power-up, or after the SBC wakes
When the SBC is mounted on the same printed circuit
At SBC power-up the V
The Watchdog software can be disabled through SPI. To
To download software into the application memory (MCU
Debug Mode
Batfail
VDD1
VSUP
SPI
TIM1(Step 3)
DD1
MCR(Step4)
voltage is provided, but if no
MCR (Step5)
Figure 11. Debug Mode Enter
SPI: Read Batfail
SBC in Debug Mode, No WD
DD1
to
• Step 2–Power-up the SBC (The BATFAIL bit is set,
• Step 3–Write to TIM1 register allowing SBC entering
• Step 4–Write to MCR register with data 0000, enabling the
• Step 5–Write to MCR register normal debug (0001x101)
• Step 6–To leave the Debug mode, write 0000 to MCR
having to clear the WD on a regular basis to facilitate
software and hardware debug.
5 should be completed consecutively and within the 350 ms
time period of the Normal Request mode. If this step is not
accomplished in a timely manner, the SBC will go into Reset
mode, entering Normal Request again.
or Sleep Debug, when a wake-up occurs the SBC enters
Normal Request mode for a time period of 350 ms. To avoid
the SBC generating a reset (enter Reset mode) the desired
next Debug mode (Normal Debug or Standby Debug) should
be configured within the 350 ms time period of the Normal
Request mode. For details, please refer to State Machine in
Debug mode,
BATFAIL bit (MCR read) and write 0000 into MCR.
illustrates the Debug mode enter.
applying the correct signal to reset pins. No function of the
SBC is operating.
device from VDD1 pin biases the VSUP pin. Therefore, V
should not be forced to a value above 5.0 V. The Reset pin is
periodically pulled low for RST
before being pulled to V
time reset is low, the reset pin sinks 5.0 mA maximum (L
parameter).
allowing the SBC to enter Normal Request mode)
Normal mode
Debug mode. Complete SPI byte: 000 1 0000
register
While in Debug mode, the SBC can be used without
At Step 2, the SBC is in Normal Request. Steps 3, 4, and
When the SBC is in Debug mode, and set in Stop Debug
To avoid entering Debug mode after a power-up, first read
Due to pass transistor from VDD1 to VSUP, supplying the
MCR (Step6)
Figure
SBC Not in Debug Mode and WD ON
16.
Analog Integrated Circuit Device Data
DD1
for 350 ms typical. During the
DUR
time (3.4 ms typical)
Freescale Semiconductor
Figure 15
PDW
SUP