LTC4305IDHD#TRPBF Linear Technology, LTC4305IDHD#TRPBF Datasheet - Page 11

• Manufacturer Part Number: LTC4305IDHD#TRPBF
• Description: IC BUFFER BUS 2WR ADDRESS 16-DFN
• Manufacturer: Linear Technology

Specifications of LTC4305IDHD#TRPBF

• Applications: Multiplexer with Amplifier
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 2.2 V ~ 5.5 V
• Package / Case: 16-DFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATIO
separated by the series combination of their switches’ on
resistances. While neither, either or both downstream
buses may be connected at the same time, logic high
levels are corrupted if both downstream buses are active
and both the V
voltage are larger than the pull-up supply voltage of the
other downstream bus. An example of this issue is shown
in Figure 1. During logic highs, DC current flows from
V
R2 and into V
current to be sourced into V
do not activate bus 1 when bus 2 is active.
Rise Time Accelerators
The Upstream Accelerators Enable and Downstream Ac-
celerators Enable bits of register 1 activate the upstream
and downstream rise time accelerators, respectively. When
activated, the accelerators turn on in a controlled manner
and source current into the pins during positive bus
transitions.
When no downstream buses are connected, an upstream
accelerator turns on when its pin voltage exceeds 0.8V
and is rising at a minimum slew rate of 0.8V/µs. When one
or more downstream buses are connected, the accelera-
tor on a given pin turns on when these conditions are met:
BUS1
through the series combination of R1, N1, N2 and
Figure 1. Example of Unacceptable Level Shifting
BUS2
CC
voltage and one downstream bus pull-up
U
N1
N2
, causing the SDA1 voltage to drop and
BUS2
SDA1
SDA2
. To avoid this problem,
V
CC
V
BUS2
= V
BUS1
= 2.5V
4305 F01
R1
10k
R2
10k
= 5V
first, the pin’s voltage is rising at a minimum slew rate of
0.8V/µs; second, the voltages on both the upstream bus
and the connected downstream buses exceed 0.8V.
Note that a downstream bus must be connected to the
upstream bus in order for its rise time accelerator current
to be active. See the Applications Section for choosing a
bus pull-up resistor value to ensure that the rise time
accelerator switches turn on. Do not activate boost cur-
rents on a bus whose pull-up supply voltage V
Doing so would cause the boost currents to source
current from V
edges.
Downstream Bus Connection Fault
By default, the LTC4305 will only connect to downstream
buses whose SDA and SCL pins are both high (above 1V)
at the moment that it receives the connection command.
In this case, the LTC4305 sets the Failed Connection
Attempt bit of register 0 low and pulls the ALERT low when
the master tries to connect to a low downstream bus. Note
that users can write a high to the Connection Requirement
bit of register 2 to program the LTC4305 to connect to
downstream buses regardless of their logic state at the
moment of connection. In this case, the Downstream
Channel Connection Fault never occurs.
Stuck Low Timeout Fault
The Stuck Low Timeout Circuitry monitors the two com-
mon internal nodes of the downstream SDA and SCL
switches and runs a timer whenever either of the internal
node voltages is below 0.52V. The timer is reset whenever
both internal node voltages are above 0.6V. If the timer
ever reaches the time programmed by Timeout Mode Bits
1 and 0 of register 2, the LTC4305 pulls ALERT low and
CC
into the V
BUS
supply during rising
LTC4305
BUS
11
< V
4305f
CC
.