DS2406+ Maxim Integrated Products, DS2406+ Datasheet
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DS2406+
Specifications of DS2406+
Related parts for DS2406+
DS2406+ Summary of contents
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... BOTTOM VIEW PIN DESCRIPTION TO-92 Pin 1 Ground Pin 2 Data Pin 3 PIO-A Pin 4 --- Pin 5 --- Pin 6 --- ORDERING INFORMATION DS2406+ DS2406+T&R DS2406P+ DS2406P+T&R + Indicates lead-free compliance DS2406 Plus 1Kb Memory 6-PIN TSOC PACKAGE TOP VIEW SIDE VIEW See Mech. Drawings Section TSOC Ground Data ...
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ADDRESSABLE SWITCH DESCRIPTION The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor’s output via the 1-Wire bus for closed loop ...
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OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2406. The device has four major data components: 64-bit lasered ROM, 1024 bits of EPROM data memory, status memory, and the ...
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PARASITE POWER The DS2406 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor during periods of time when the signal line is high. During low times the device continues to operate off of ...
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MEMORY MAP The DS2406 has two memory sections, called data memory and status memory. The data memory consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. The address range of the device’s status ...
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STATUS MEMORY The Status Memory can be read or written to indicate various conditions to the software interrogating the DS2406. These conditions include special features for the data memory, definition of the settings for the Conditional Search as well as ...
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Status Memory location 7 serves three purposes holds the selection code for the Conditional Search function, 2) provides the bus master a memory mapped access to the channel flip-flops that control the PIO output transistors, and 3) allows ...
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Extended Read Memory [A5h] The Extended Read Memory command supports page redirection when reading data from the 1024-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master ...
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WRITING EPROM MEMORY The function flow for writing to the Data Memory and Status Memory is almost identical. After the appropriate write command has been issued, the bus master will send a two-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte ...
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Memory Function Flow Chart Figure 7 Bus Master TX Memory Function Command F0h Read Memory ? Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Bus Master RX Data from Data Memory DS2406 Master increments TX Reset ...
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Memory Function Flow Chart (continued) Figure 7 From Figure 7 1st Part 0Fh Write Memory ? Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Bus Master TX Data Byte (D7:D0) Bus Master RX CRC16 of Command, ...
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Memory Function Flow Chart (continued) Figure 7 From Figure 7 2nd Part AAh Read Status ? Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Status Address = (T15:T0) Bus Master RX Data from Status Memory DS2406 Master increments TX Reset ...
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Write Memory [0Fh] The Write Memory command is used to program the 1024-bit EPROM data memory. The details of the functional flow chart are described in the section “Writing EPROM Memory”. The data memory address range is 0000h to 007Fh. ...
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Most easily understood are the bits CHS0 and CHS1, which select the channels to communicate with. One can select one of the two channels or both channels together. The selection codes are shown in the table below. CHS1 When reading ...
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The TOG bit of Channel Control Byte 1 specifies if one is always reading or writing (TOG = one is going to change from reading to writing or vice versa after every data byte that has been ...
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After the Channel Control bytes have been transmitted the bus master receives the Channel Info byte (Figure 9). This byte indicates the status of the channel flip-flops, the PIO pins, the activity latches as well as the availability of channel ...
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TWO-CHANNEL WRITE Figure 10c 15 µs < td1 < 60 µs td1 1-WIRE A1 B1 IC=1, SYNCHRONOUS MODE PIO-A A1 PIO-B B1 IC=0, ASYNCHRONOUS MODE PIO-A A1 PIO-B B1 1-WIRE BUS SYSTEM The 1-Wire bus is a system, which has ...
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DS2406 EQUIVALENT CIRCUIT Figure 11 1-Wire Interface DATA 5 µA Typ. MOSFET Ground BUS MASTER CIRCUIT Figure 12 A) Open Drain V DD BUS MASTER DS5000 OR 8051- EQUIVALENT Open Drain Port Pin RX TX The interface is reduced to ...
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INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus ...
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ROM FUNCTIONS FLOW CHART Figure 13 33h 55h N Read ROM Match ROM Command Command ? Y DS2406 TX Master TX Bit 0 Family Code (1 Byte) Bit 0 Match ? DS2406 TX Master TX Bit 1 Serial Number (6 ...
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Conditional Search ROM [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. This command provides an efficient means for the bus master to ...
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The activity latch (Figure 11) captures an event for interrogation by the bus master at a later time. This way, the bus master needs not interrogate devices continuously. The activity latch is set to 1 with the first negative or ...
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SIGNALING The DS2406 requires strict protocols to ensure data integrity. The protocol consists of five types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data, and Program Pulse. Except ...
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READ/WRITE TIMING DIAGRAM Figure 15 Write-one Time Slot V PULLUP V PULLUP MIN V IH MIN V IL MAX 0V RESISTOR MASTER Write-zero Time Slot V PULLUP V PULLUP MIN V IH MIN V IL MAX 0V RESISTOR MASTER t ...
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READ/WRITE TIMING DIAGRAM (continued) Figure 15 Read-data Time Slot V PULLUP V PULLUP MIN V IH MIN V IL MAX 0V RESISTOR MASTER DS2406 * The optimal sampling point for the master is as close as possible to the end ...
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PROGRAM PULSE TIMING DIAGRAM Figure PULLUP GND Normal 1-Wire > 5 µs Communication Ends LINE TYPE LEGEND: Bus master active high ( mA) Resistor pull-up CRC GENERATION With the DS2406 there are two ...
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CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on DATA or PIO-A to Ground Voltage PIO-B to Ground CC Operating Temperature Range Storage Temperature Range Soldering Temperature * This is a stress rating only and functional operation of the device at ...
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CAPACITANCES PARAMETER Capacitance DATA Pin Capacitance PIO-A Pin Capacitance PIO-B Pin Capacitance V Pin CC AC ELECTRICAL CHARACTERISTICS PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup ...
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PIO SINK CURRENT 100 NOTE: The sink current is production-tested ...
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Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 2µs of this falling edge and will remain valid for 15µs total ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any MAXIM is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation. DESCRIPTION specification from headline to Data Pin parameter block in the spec from 0 ...