CYV15G0101EQ-SXC Cypress Semiconductor Corp, CYV15G0101EQ-SXC Datasheet - Page 4

• Manufacturer Part Number: CYV15G0101EQ-SXC
• Description: IC CABLE EQUALIZER 16SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0101EQ-SXC

• Applications: Video
• Interface: Serial
• Voltage - Supply: 3.135 V ~ 3.465 V
• Package / Case: 16-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Equalizer Operation
The CYV15G0101EQ is a high speed adaptive cable equalizer
designed to equalize standard definition (SD) and high definition
(HD) serial digital interface (SDI) video data streams.
CYV15G0101EQ equalizer is optimized to equalize up to 350m
of Canare L-5CFB and Belden 1694A cable at 270 Mbps and
typically up to 200m of Canare L-5CFB and Belden 1694A cable
at 1.485 Gbps. The CYV15G0101EQ equalizer contains one
power supply and typically consumes 160 mW power at 3.3V.
The multi rate equalizer meets the SMPTE 259M, SMPTE 292M,
SMPTE 344M, and DVB-ASI video standards. It meets all patho-
logical requirements for SMPTE 292M as defined by RP198, and
for SMPTE 259M as defined by RP178. The CYV15G0101EQ
multi rate cable equalizer is auto adaptive from 143 Mbps to
1.485 Gbps.
The CYV15G0101EQ equalizer has variable gain and multiple
equalization stages that reverse the effects of the cable. This
equalization is achieved by separate regulation of the lower and
higher frequency components in the signal to give a clean output
eye diagram. The CYV15G0101EQ has DC restoration to
compensate for the DC content of the SMPTE pathological
patterns.
SDI, SDI
The CYV15G0101EQ accepts single-ended or differential serial
video data streams over 75Ω coaxial cable. It is recommended
to AC couple the SDI and SDI inputs as they are internally biased
to 1.2V.
SDO, SDO
The CYV15G0101EQ has differential serial output interface
drivers that use current mode logic (CML) drivers to provide
source matching for the transmission line. These outputs are
either AC coupled or DC coupled to the HOTLink II SerDes
device.
CLI
Cable Length Indicator (CLI) is an analog output that gives an
output voltage proportional to the equalized cable length. CLI
gives an approximation of the length of cable at the differential
serial inputs (SDI, SDI). CLI works at high definition (HD) data
rates and standard definition (SD) data rates. The graph in
Figure 3
Belden 1694A cable lengths. With an increase in cable length,
CLI output voltage decreases.
Document Number: 001-04184 Rev. *E
on page 7 illustrates the CLI output voltage at various
MCLADJ
Maximum Cable Length Adjust (MCLADJ) sets the approximate
maximum amount of cable to be equalized. When the maximum
cable length set by MCLADJ is reached, CD is driven high and
the outputs are muted. MCLADJ works at SD and HD data rates.
The graph in
at MCLADJ input to equalize various Belden 1694A cable
lengths for SD and HD data rates. If MCLADJ functionality is not
needed, this pin should be left floating or tied to ground to allow
maximum equalized cable length.
CD/MUTE
Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that
provides an indication of the signal present at the equalizer’s
input, or it controls the muting of the equalizer’s output. The
(CD/MUTE) operates for both HD and SD data rates.
If CD/MUTE is used as an output and the incoming data stream
is not present or the cable length exceeds that set by MCLADJ,
the voltage at the CD/MUTE output is greater than 2.8V. If
CD/MUTE is used as an output, the incoming data stream is
present and the cable length does not exceed that set by
MCLADJ, then the voltage at the CD/MUTE output is less than
0.8V.
If CD/MUTE is used as an input and is set LOW, the equalizer
serial outputs are not muted. If the CD/MUTE is used as an input
and is set HIGH, then the equalizer serial outputs are muted.
When an invalid signal or a signal transmitted with a launch
amplitude of less than 500 mV at HD data rates is received, the
equalizer’s serial outputs are muted.
BYPASS
The CYV15G0101EQ has a bypass mode that allows the user to
bypass the equalizer’s equalization and DC restoration
functions. When the bypass mode is set HIGH, the signal
presented at the equalizer’s differential serial inputs (SDI, SDI)
is routed to the equalizer’s differential serial outputs (SDO, SDO)
without equalizing.
When BYPASS is set LOW, the incoming video data stream is
equalized and presented at the equalizer‘s differential serial
outputs (SDO, SDO).
In equalizer bypass mode, CD/MUTE is not functional.
AGC
Place a capacitor of 1 μF between the AGC± pins of the
CYV15G0101EQ equalizer.
Figure 2
on page 7 illustrates the voltage required
CYV15G0101EQ
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