DS92001TMA/NOPB National Semiconductor, DS92001TMA/NOPB Datasheet - Page 4

• Manufacturer Part Number: DS92001TMA/NOPB
• Description: IC BLVDS-BLVDS BUFFER 3.3V 8SOIC
• Manufacturer: National Semiconductor
• Type: Bufferr

Specifications of DS92001TMA/NOPB

• Tx/rx Type: LVDS
• Delay Time: 2.0ns
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 65mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Supply Current: 20µA
• Supply Voltage Range: 3V To 3.6V
• Driver Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Voltage, Vcc: 4V
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate: 400Mbps
• Data Rate Max: 400Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Capacitance - Input: -
• Other names: *DS92001TMA; *DS92001TMA/NOPB; DS92001TMA

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LVDS OUTPUT AC SPECIFICATIONS (OUT)
t
t
t
t
t
t
t
t
t
t
t
t
t
f
Symbol
PHLD
PLHD
SKD1
SKD3
SKD4
LHT
HLT
PHZ
PLZ
PZH
PZL
DJ
RJ
MAX
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
V
Note 3: All typical are given for V
Note 4: Output short circuit current (I
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and
temperature) range.
Note 6: t
the same channel (a measure of duty cycle).
Note 7: t
applies to devices at the same V
Note 8: t
operating temperature and voltage ranges, and across process distribution. t
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following
test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent
86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t
60 picoseconds.
Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz
= 50Ω, tr, tf
Note 11: f
is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum
guaranteed AC frequency. The typical value is always greater than the minimum guarantee.
TH
, V
TL
, and ΔV
SKD4
SKD1
SKD3
MAX
Differential Propagation Delay
High to Low
(Note 10)
Differential Propagation Delay
Low to High
(Note 10)
Pulse Skew |t
(measure of duty cycle)
(Notes 5, 6)
Part-to-Part Skew (Notes 5, 7)
Part-to-Part Skew (Notes 5, 8)
Rise Time (Notes 5, 10)
20% to 80% points
Fall Time (Notes 5, 10)
80% to 20% points
Disable Time (Active High to Z)
Disable Time (Active Low to Z)
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
LVDS Data Jitter, Deterministic
(Peak-to-Peak) (Note 9)
LVDS Clock Jitter, Random (Note
9)
Maximum guaranteed frequency
(Note 11)
≤
, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended
, |t
, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD
0.5ns. Generator used was HP8130A (300MHz capability).
PLHD
OD
. V
− t
OD
PHLD
Parameter
has a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
CC
CC
− t
and within 5°C of each other within the operating temperature range. This parameter guaranteed by design and characterization.
= +3.3V and T
PHLD
OS
) is specified as magnitude only, minus sign indicates direction only.
|
A
= +25°C, unless otherwise stated.
V
R
Figure 3 and Figure 4
R
Figure 3 and Figure 5
R
Figure 6 and Figure 7
V
400Mbps (NRZ)
V
V
ID
ID
ID
ID
L
L
L
= 27Ω or 50Ω, C
= 50Ω or 27Ω, C
= 50Ω, C
= 200mV, V
= 300mV; PRBS = 2
= 300mV; V
= 200mV, V
L
= 15pF
CM
CM
CM
= 1.2V,
= 1.2V at 200MHz clock
= 1.2V
SKD4
L
L
Conditions
4
= 15pF
= 15pF
is defined as |Max − Min| differential propagation delay.
23
− 1 data; V
CM
≥
200mV, Duty Cycle better than 45/55%. This specification
= 1.2V at
DJ
measured 100 picoseconds, t
0.350
0.350
Min
200
1.0
1.0
0
0
0
Typ
200
100
100
300
1.4
1.4
0.6
0.6
20
3
3
≤
f
Max
200
300
120
120
≤
2.0
2.0
1.0
1.0
RJ
25
25
78
36
1
200MHz, Zo
measured
ID
, V
Units
MHz
OD
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ps
ps
,