MAX3880ECB+D Maxim Integrated Products, MAX3880ECB+D Datasheet
MAX3880ECB+D
Specifications of MAX3880ECB+D
Related parts for MAX3880ECB+D
MAX3880ECB+D Summary of contents
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... TTL *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z ________________________________________________________________ Maxim Integrated Products For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. +3.3V, 2.488Gbps, SDH/SONET ♦ ...
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SDH/SONET 1:16 Deserializer with Clock Recovery ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (V )...............................-0.5V to +7.0V CC Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-, SYNC+, SYNC-)........................... (V CC Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA Voltage at LOL, ...
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Deserializer with Clock Recovery AC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V, differential loads = 100Ω ±1 +3.3V +25°C.) (Note PARAMETER SYMBOL Serial Data Rate Parallel Output Data Rate Parallel ...
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SDH/SONET 1:16 Deserializer with Clock Recovery (V = +3.3V +25°C, unless otherwise noted RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT) MAX3880-01 DATA PATTERN CLOCK 1.64ns/div JITTER TOLERANCE vs. INPUT VOLTAGE 0.8 ...
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Deserializer with Clock Recovery PIN NAME 1, 17, 25, 33, 41, 49, 56, GND Ground 62 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 3 FIL- Negative Filter Input. ...
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SDH/SONET 1:16 Deserializer with Clock Recovery V CC 50Ω SDI+ AMP SDI- MUX SLBI+ AMP SLBI- 50Ω SIS SYNC- LVDS 100Ω SYNC+ Figure 3. MAX3880 Functional Diagram Detailed Description The MAX3880 deserializer with clock recovery converts ...
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Deserializer with Clock Recovery dropped, shifting the alignment between PCLK and data by 1 bit. The SYNC signal must be at least four serial bit periods wide (4 x 402ps). See Figure 4 for the timing diagram and Figure ...
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SDH/SONET 1:16 Deserializer with Clock Recovery PCLK t CLK-Q PD0–PD15 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK = (PCLK+) - (PCLK-). Figure 5. Timing Parameters Low-Voltage Differential-Signal (LVDS) Inputs and Outputs The MAX3880 features LVDS inputs and ...
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Deserializer with Clock Recovery Interfacing with PECL Input Levels When interfacing with differential PECL input levels important to attenuate the signal while still maintaining 50Ω termination (Figure 7). AC-coupling is also required to maintain the input common-mode ...
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SDH/SONET 1:16 Deserializer with Clock Recovery TOP VIEW GND 1 FIL+ 2 FIL PHADJ+ 5 PHADJ SDI+ 8 SDI SLBI+ 11 SLBI ...
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Deserializer with Clock Recovery (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) ______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET Package Information PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Package Information (continued) Printed USA is a registered trademark of Maxim Integrated Products, Inc ...