MAX9218ETM+ Maxim Integrated Products, MAX9218ETM+ Datasheet

IC DESERIALIZER LVDS 48-TQFN

MAX9218ETM+

Manufacturer Part Number
MAX9218ETM+
Description
IC DESERIALIZER LVDS 48-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX9218ETM+

Function
Deserializer
Data Rate
700Mbps
Input Type
LVDS
Output Type
LVCMOS
Number Of Inputs
1
Number Of Outputs
27
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TQFN Exposed Pad
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX9218 digital video serial-to-parallel converter
deserializes a total of 27 bits during data and control
phases. In the data phase, the LVDS serial input is con-
verted to 18 bits of parallel video data and in the control
phase, the input is converted to 9 bits of parallel control
data. The separate video and control phases take
advantage of video timing to reduce the serial data rate.
The MAX9218 pairs with the MAX9217 serializer to form
a complete digital video transmission system.
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9218 features a selec-
table rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±30kV air discharge.
The MAX9218 operates from a +3.3V core supply and
features a separate output supply for interfacing to 1.8V
to 3.3V logic-level inputs. This device is available in 48-
lead Thin QFN and LQFP packages and is specified
from -40°C to +85°C.
19-3557; Rev 5; 8/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
TOP VIEW
Navigation System Display
In-Vehicle Entertainment System
Video Camera
LCD Displays
RGB_OUT10
RGB_OUT11
RGB_OUT12
RGB_OUT13
RGB_OUT14
RGB_OUT15
RGB_OUT16
RGB_OUT17
RGB_OUT8
RGB_OUT9
V
CCO
V
GND
CCO
________________________________________________________________ Maxim Integrated Products
37
38
39
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41
42
43
44
45
46
47
48
+
General Description
MAX9218
LQFP
Applications
DC-Balanced LVDS Deserializer
24
23
22
21
20
19
18
17
16
15
14
13
DE_OUT
CNTL_OUT8
CNTL_OUT7
CNTL_OUT6
CNTL_OUT5
CNTL_OUT4
CNTL_OUT3
CNTL_OUT2
CNTL_OUT1T
OUTEN
PWRDWN
CNTL_OUT0
♦ Proprietary Data Decoding for DC Balance and
♦ Control Data Deserialized During Video Blanking
♦ Five Control Data Inputs Are Single Bit-Error
♦ Output Transition Time Is Scaled to Operating
♦ Staggered Output Switching Reduces EMI
♦ Output Enable Allows Busing of Outputs
♦ Clock Pulse Stretch on Lock
♦ Wide ±2% Reference Clock Tolerance
♦ Synchronizes to MAX9217 Serializer Without
♦ ISO 10605 ESD Protection
♦ Separate Output Supply Allows Interface to 1.8V
♦ +3.3V Core Power Supply
♦ Space-Saving Thin QFN and LQFP Packages
♦ -40°C to +85°C Operating Temperature
+ Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
* EP = Exposed pad.
27-Bit, 3MHz-to-35MHz
MAX9218ECM+
MAX9218ECM/V+
MAX9218ETM+
Reduced EMI
Tolerant
Frequency for Reduced EMI
External Control
to 3.3V Logic
RGB_OUT10
RGB_OUT11
RGB_OUT12
RGB_OUT13
RGB_OUT14
RGB_OUT15
RGB_OUT16
RGB_OUT17
RGB_OUT8
RGB_OUT9
V
PART
CCO
V
GND
CCO
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48
+
THIN QFN-EP
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP RANGE
Ordering Information
MAX9218
Pin Configurations
48 LQFP
48 LQFP
48 Thin QFN-EP*
PIN-PACKAGE
24
23
22
21
20
19
18
17
16
15
14
13
Features
DE_OUT
CNTL_OUT8
CNTL_OUT7
CNTL_OUT6
CNTL_OUT5
CNTL_OUT4
CNTL_OUT3
CNTL_OUT2
CNTL_OUT1
CNTL_OUT0
OUTEN
PWRDWN
1

Related parts for MAX9218ETM+

MAX9218ETM+ Summary of contents

Page 1

... Separate Output Supply Allows Interface to 1.8V to 3.3V Logic ♦ +3.3V Core Power Supply ♦ Space-Saving Thin QFN and LQFP Packages ♦ -40°C to +85°C Operating Temperature Applications PART MAX9218ECM+ MAX9218ECM/V+ MAX9218ETM+ + Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part Exposed pad. DE_OUT 24 23 CNTL_OUT8 V ...

Page 2

DC-Balanced LVDS Deserializer ABSOLUTE MAXIMUM RATINGS V to _GND........................................................-0.5V to +4.0V CC_ Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDS GND...........................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDS GND or V IN+, IN- Short ...

Page 3

DC ELECTRICAL CHARACTERISTICS (continued) = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐V (V CC_ - ⏐ /2⏐ -40°C to +85°C, unless otherwise noted. Typical values are ...

Page 4

DC-Balanced LVDS Deserializer AC ELECTRICAL CHARACTERISTICS = 8pF, PWRDWN = high, differential input voltage ⏐ +3.0V to 3.6V, C CC_ L = ⏐V - ⏐V V /2⏐ /2⏐ -40°C to +85°C, unless ...

Page 5

C = 8pF +25°C, unless otherwise noted WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY FREQUENCY (MHz) OUTPUT TRANSITION TIME ...

Page 6

DC-Balanced LVDS Deserializer PIN NAME Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low ...

Page 7

IN+ IN- RNG0 PLL RNG1 TIMING AND CONTROL IN 1. IN- Figure 1. LVDS Input Bias PCLK_OUT ODD RGB_OUT CNTL_OUT EVEN RGB_OUT CNTL_OUT RISING LATCH EDGE SHOWN (R/F = HIGH). Figure 2. Worst-Case Output Pattern _______________________________________________________________________________________ ...

Page 8

DC-Balanced LVDS Deserializer PCLK_OUT PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) DE_OUT LOCK RGB_OUT[17:0] CNTL_OUT[8:0] Figure 5. Synchronous Output Timing 20 SERIAL BITS SERIAL-WORD N IN+, IN- PCLK_OUT CNTL_OUT RGB_OUT Figure 6. Deserializer Delay 8 _______________________________________________________________________________________ ...

Page 9

PWRDWN REFCLK HIGH IMPEDANCE PCLK_OUT RGB_OUT CNTL_OUT HIGH IMPEDANCE DE_OUT HIGH IMPEDANCE LOCK NOTE: R/F = HIGH Figure 7. PLL Lock to REFCLK and Power-Down Delay OUTEN 0. DE_OUT LOCK RGB_OUT[17:0] HIGH-Z CNTL_OUT[8:0] Figure 8. Output Enable ...

Page 10

DC-Balanced LVDS Deserializer Detailed Description The MAX9218 DC-balanced deserializer operates at a parallel clock frequency of 3MHz to 35MHz, deserializ- ing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data ...

Page 11

RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL RNG1 PWRDWN MAX9217 CERAMIC RF SURFACE-MOUNT CAPACITOR Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link RGB_IN 1 0 CNTL_IN DE_IN PCLK_IN TIMING AND RNG0 PLL CONTROL ...

Page 12

DC-Balanced LVDS Deserializer Input Frequency Detection A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, ...

Page 13

Staggered and Transition Time Adjusted RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are ...

Page 14

DC-Balanced LVDS Deserializer The MAX9218 ESD tolerance is rated for the Human Body Model, Machine Model, and ISO 10605. ISO 10605 specifies ESD tolerance for electronic systems 1MΩ 1.5kΩ CHARGE-CURRENT- DISCHARGE LIMIT RESISTOR RESISTANCE HIGH- C ...

Page 15

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 © 2009 Maxim Integrated Products ...

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