MAX9236EUM+D Maxim Integrated Products, MAX9236EUM+D Datasheet - Page 11

• Manufacturer Part Number: MAX9236EUM+D
• Description: IC LVDS DESERIAL 21BIT 48-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9236EUM+D

• Function: Deserializer
• Data Rate: 1.386Gbps
• Input Type: LVDS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 3
• Number Of Outputs: 21
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
where:
C = AC-coupling capacitor (F).
t
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
R
R
Equation 1 is for two series capacitors (Figure 10). The
bit time (t
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 11).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
Jitter due to droop is proportional to the droop and
transition time:
where:
t
t
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 11) is:
The inverting and noninverting LVDS inputs are internally
connected to +1.2V through 42kΩ (min) to provide bias-
ing for AC-coupling (Figure 1). A frequency-detection
circuit on the clock input detects when the input is not
switching, or is switching at low frequency. In this case,
all outputs are driven low. To prevent switching due to
noise when the clock input is not driven, bias the clock
input to differential +15mV by connecting a 10kΩ ±1%
B
J
T
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
T
O
= jitter (s).
= transition time (s) (0 to 100%).
C = - (2 x t
C = - (4 x t
= bit time (s).
= termination resistor (Ω).
= output resistance (Ω).
C = - (2 x t
Input Bias and Frequency Detection
B
) is the period of the parallel clock divided by
B
B
Hot-Swappable, 21-Bit, DC-Balanced LVDS
x DSV) / (ln (1 - D) x (R
x DSV) / (ln (1 - D) x (R
B
______________________________________________________________________________________
x DSV) / (ln (1 - D) x (R
t
J
t
C = 0.0773µF
J
= t
= 1ns x 0.02
t
J
T
= 20ps
x D (Eq 2)
T
T
+ R
+ R
T
O
+ R
O
)) (Eq 1)
)) (Eq 3)
O
))
pullup resistor between the noninverting input and V
and a 10kΩ ±1% pulldown resistor between the invert-
ing input and ground. These bias resistors, along with
the 100Ω ±1% tolerance termination resistor, provide
+15mV of differential input.
At each unused LVDS data input, pull the inverting input
up to V
input down to ground using a 10kΩ resistor. Do not con-
nect a termination resistor. The pullup and pulldown resis-
tors drive the corresponding outputs low and prevent
switching due to noise.
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock-time specification. When the PLL is locking, the
outputs are low.
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
CC
, V
CC
CCO
using a 10kΩ resistor, and pull the noninverting
, PLL V
Input Clock and PLL Lock Time
CC
, and LVDS V
Unused LVDS Data Inputs
Deserializers
Power-Supply Bypassing
Cables and Connectors
CC
pin with high-fre-
PWRDWN
CC
11
,