ADM1022ARQ-REEL ON Semiconductor, ADM1022ARQ-REEL Datasheet - Page 15

• Manufacturer Part Number: ADM1022ARQ-REEL
• Description: IC SENSOR TEMP/DET 3/5.5V 16QSOP
• Manufacturer: ON Semiconductor
• Type: Temperature Sensorr

Specifications of ADM1022ARQ-REEL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Analog
• Interface: Serial
• Current - Supply: 2.6mA
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

5 V OPERATION
The ADM1022 may be operated with V
nected to any supply voltage between 3.0 V and 5.5 V, but it
should be noted that the reset threshold voltages are fixed and
optimized for 3.3 V operation. If the V
for example, the V
3.3 V supply without problems. However, the reset threshold for
the 5 V, V
operate reliably and may not give a reliable indication of brown-
out on the 5 V supply.
Alternatively, V
age higher than 3.3 V by adding an input attenuator.
The ratio of R1 to R2 is given by:
Where V
reset voltage of the V
The input resistance of the V
with a tolerance of around ± 30%, so the parallel combination of
R1 and R2 should be much lower than 100 kΩ to minimize
errors due to variations in this input resistance.
INITIALIZATION (SOFT RESET)
Soft reset performs a similar, but not identical, function to
power-on reset. The Test Register and Analog Output register
are not initialized.
Soft reset is accomplished by setting Bit 4 of the Configuration
Register high. This bit automatically clears after being set.
NAND TREE TEST
A NAND tree is provided in the ADM1022 for Automated Test
Equipment (ATE) board level connectivity testing. The device
is placed into NAND tree test mode by powering up with pin
FAN_SPD/NTEST_IN (Pin 8) held high. This pin is sampled
and its state at power-up is latched. If it is connected high, the
NAND tree test mode is invoked. NAND tree test mode will
only be exited once the ADM1022 is powered down.
In NAND tree test mode, all digital inputs may be tested as illus-
trated in Table III. ADD/NTEST_OUT will become the NAND
tree output pin.
R
CC
is the desired reset voltage and 2.93 V is the nominal
supply, may be below that at which 5 V logic will
MON
MON
R1/R2 = (V
may be configured to monitor a supply volt-
MON
input can still be used to monitor another
V
IN
input.
MON
R1
R
– 2.93)/2.93
R2
input is approximately 100 kΩ,
V
MON
CC
CC
supply voltage is 5 V,
and/or V
MON
con-
The structure of the NAND Tree is shown in Figure 21. To
perform a NAND Tree test, all pins are initially driven low. The
test vectors set all inputs low, then one-by-one toggles them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the out-
put of the tree, cycling towards the farthest, causes the output of
the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns.
GPI
0
0
0
0
1
CONFIGURING THE INTERRUPT
On power-up, the Interrupt functionality of the device is disabled.
The Configuration Register (0x40) must be written to, in order
to enable the Interrupt output. The INT_Clear bit (Bit 2) should
be cleared to 0 and the INT_Enable bit (Bit 1) of the Register
should be set to 1.
If the INT_Enable bit is set, and the INT_Clear bit is not
cleared to 0, then any interrupts generated will be reflected in
the Interrupt Status Register, but will not toggle the Interrupt
pin externally.
FAN_SPD/
NTEST_IN
SDA
SCL
GPI
MR
SCL
0
0
0
1
1
D
POWER-ON
LATCH
RESET
Table III. Test Vectors
SDA
0
0
1
1
1
CLK
Q
ENABLE
MR
0
1
1
1
1
ADD/NTEST_OUT
1
0
1
0
1
ADD/NTEST_OUT
ADM1022