AD9949KCPRL Analog Devices Inc, AD9949KCPRL Datasheet - Page 24

IC CCD SIGNAL PROCESSOR 40-LFCSP

AD9949KCPRL

Manufacturer Part Number
AD9949KCPRL
Description
IC CCD SIGNAL PROCESSOR 40-LFCSP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet

Specifications of AD9949KCPRL

Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Sample Rate
36MSPS
Input Voltage Range
0.5V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Resolution
12b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
40
Package Type
LFCSP EP
Number Of Channels
1
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant
AD9949
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD falling edge. The PxGA steering is synchronized with the reset of the
internal H-Counter (see Figure 26).
As mentioned in the H-Counter Behavior section, the AD9949 H-counter rolls over to zero and continues counting when the maximum
counter length is exceeded. The newer AD9949A product does not roll over but holds at its maximum value until the next HD rising edge
occurs.
(PIXEL COUNTER)
H-COUNTER
PxGA GAIN
REGISTER
CLI
HD
VD
NOTES
1. INTERNAL H-COUNTER IS RESET 7 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H-COUNTER
Figure 26. H-Counter Synchronization
RESET
X
X
0
0
Rev. B | Page 24 of 36
1
1
2
0
3
1
4
0
5
1
6
0
7
1
8
0
9
1
10
0
11
1
12
0
14
1
15
0
0
2
1
3
2
2
3
3

Related parts for AD9949KCPRL