AD9846AJST Analog Devices Inc, AD9846AJST Datasheet
AD9846AJST
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AD9846AJST Summary of contents
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PBLK CCDIN CLPDM AUX1IN AUX2IN CLP AD9846A PxGA is a registered trademark of Analog Devices, Inc. PRODUCT DESCRIPTION The AD9846A is a complete analog signal processor for CCD applications. It features a 30 MHz single-channel architecture designed to sample ...
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AD9846A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale ...
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CCD-MODE SPECIFICATIONS Parameter P OWER CONSUMPTION MAXIMUM CLOCK RATE CDS Gain 1 Allowable CCD Reset Transient 1 Max Input Range Before Saturation 1 Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control ...
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AD9846A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS ...
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... SHD t 4 CDM t 2 COB INH 7 SCLK Model Unit AD9846AJST –20°C to +85° THERMAL CHARACTERISTICS V Thermal Resistance V 48-Lead LQFP Package V θ = 92° °C 150 °C 300 AD9846A Typ Max Unit 33 ns 16.7 ns 8 Pixels 20 Pixels 8.3 ns 16 14.5 ...
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AD9846A CONNECT Pin Number Name 3–12 D0–D9 13 DRVDD 14 DRVSS 15, 41 DVSS 16 DATACLK 17 DVDD1 PBLK 20 CLPOB 21 SHP 22 SHD 23 CLPDM 24 VD 25, 26, ...
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DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit ...
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AD9846A–Typical Performance Characteristics 140 130 V = 3.3V DD 120 V = 3.0V DD 110 100 SAMPLE RATE – MHz 0.50 0.25 0 –0.25 –0.50 0 200 400 600 ...
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CCD-MODE AND AUX MODE TIMING CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT ...
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AD9846A PIXEL GAIN AMPLIFIER (PxGA) TIMING FRAME n VD 0101... 2323... LINE 0 LINE 1 HD NOTE GAIN0 GAIN1 GAIN2 GAIN3 5 PIXEL MIN VD HD SHP PxGA GAIN NOTES: 1. MINIMUM ...
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LINE n VD 012012012... HD NOTE GAIN0 GAIN1 GAIN2 5 PIXEL MIN VD 5 PIXEL MIN HD SHP PxGA GAIN NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. ...
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AD9846A VD EVEN FIELD 0101... 0101... 0101... LINE 0 LINE 1 LINE 2 HD NOTE GAIN0 GAIN1 GAIN2 GAIN3 VD 5 PIXEL MIN HD 3ns MIN SHP PxGA GAIN NOTES: 1. BOTH ...
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VD HD 3ns MIN SHP GAIN0 PxGA GAIN NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES AND SELECTS GAIN0 AND SELECTS ...
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AD9846A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name Operation Channel Select Power-Down CCD/AUX1/2 Modes VGA Gain LSB Clamp Level LSB Control 1 1 ...
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BITS OPERATION RNW ... SDATA ... SCK NOTES: 1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS ...
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AD9846A Table IV. Clamp Level Register Contents (Default Value x080) MSB D10 Table V. Control Register Contents (Default Value x000) Data Out DATACLK D10 ...
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CIRCUIT DESCRIPTION AND OPERATION The AD9846A signal processing chain is shown in Figure 25. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To reduce the large dc offset of the ...
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AD9846A MOSAIC SEPARATE COLOR CCD: PROGRESSIVE BAYER STEERING MODE LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ... LINE1 GAIN2, GAIN3, GAIN2, GAIN3 ... LINE2 GAIN0, GAIN1, GAIN0, GAIN1 ... Gb ...
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A/D Converter The AD9846A uses high-performance ADC architecture, opti- mized for high speed and low power. Differential Nonlinearity (DNL) performance is typically better than 0.5 LSB, as shown in TPC 2. Instead of the 1 V full-scale range used by ...
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AD9846A APPLICATIONS INFORMATION The AD9846A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 32, the CCD image (pixel) data is buffered and sent to the AD9846A analog input through ...
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SERIAL INTERFACE (MSB DATA OUTPUTS 3V DRIVER SUPPLY Internal Power-On Reset Circuitry After power-on, the AD9846A will automatically reset all inter- nal registers and perform internal calibration procedures. This takes approximately complete. During this time, ...
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AD9846A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 TOP VIEW (PINS DOWN) COPLANARITY 12 25 0.003 (0.08 MIN ...
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