AD9845BJSTRL Analog Devices Inc, AD9845BJSTRL Datasheet - Page 10

• Manufacturer Part Number: AD9845BJSTRL
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9845BJSTRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Current - Supply: -

AD9845B
PIXEL GAIN AMPLIFIER (PxGA) TIMING
HD
VD
HD
PxGA GAIN
VD
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
PxGA
GAIN
SHP
SHP
HD
VD
VD
HD
0101...
LINE 0
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
0101...
LINE 0
NOTES
1. MINIMUM PULSEWIDTH FOR HD AND VD IS FIVE PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SETUP TIME IS 3 ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
2323...
LINE 1
2323...
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
3ns MIN
LINE 1
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
5 PIXEL MIN
FRAME N
0101...
LINE 2
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
EVEN FIELD
LINE 2
0101...
5 PIXEL MIN
LINE M–1
LINE M–1
3ns MIN
LINE M
LINE M
–10–
GAINX
GAINX
0101...
3ns MIN
LINE 0
GAIN0
0101...
3ns MIN
LINE 0
GAIN0
GAIN1
GAIN1
2323...
LINE 1
2323...
LINE 1
ODD FIELD
GAIN0
GAIN0
FRAME N+1
0101...
LINE 2
0101...
LINE 2
GAINX
GAINX
LINE M–1
GAIN2
LINE M–1
GAIN2
GAIN3
GAIN3
LINE M
LINE M
REV. B