AD9822JRSRL Analog Devices Inc, AD9822JRSRL Datasheet - Page 17

• Manufacturer Part Number: AD9822JRSRL
• Description: IC CCD SIGNAL PROC 14BIT 28-SSOP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 14-Bitr

Specifications of AD9822JRSRL

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Current - Supply: 73mA
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Analog Front End Type: CCD/CIS
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 15MSPS
• Input Voltage Range: 1V
• Operating Supply Voltage (min): 3/4.75V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Resolution: 14b
• Supply Current: 4/73mA
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP
• Number Of Channels: 3
• Lead Free Status / RoHS Status: Not Compliant

APPLICATIONS
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 16 shows the recommended circuit configuration for
3-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 µF (see the Circuit Operation
section). A single ground plane is recommended for the
AD9822. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9822.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
DATA OUTPUTS
CLOCK INPUTS
DATA OUTPUTS
0.1µF
CLOCK INPUTS
Figure 17. Recommended Circuit Configuration, 3-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
0.1µF
5V/3V
5V/3V
3
8
3
8
Figure 16. Recommended Circuit Configuration, 3-Channel CDS Mode
10
12
13
14
11
1
2
3
4
5
6
7
8
9
10
12
13
14
11
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
3
4
5
6
7
8
9
CDSCLK1
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AD9822
AD9822
Rev. B | Page 17 of 20
OFFSET
SLOAD
SDATA
AVDD
CAPB
AVDD
AVSS
CAPT
AVSS
SCLK
OFFSET
VING
VINR
VINB
CML
SLOAD
SDATA
AVDD
CAPB
AVDD
CAPT
SCLK
AVSS
AVSS
VINR
VING
VINB
CML
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
5V
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 6 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD9822 pins. When operating in single-channel
mode, the unused analog inputs should be grounded.
Figure 17 shows the recommended circuit configuration for
3-channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9822 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 2 V (see the Circuit Operation section).
5V
0.1µF
0.1µF
3
3
SERIAL INTERFACE
SERIAL INTERFACE
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+
5V
RED INPUT
GREEN INPUT
BLUE INPUT
+
5V
0.1µF
10µF
RED INPUT
GREEN INPUT
BLUE INPUT
10µF
0.1µF
0.1µF
0.1µF
0.1µF
1.0µF
AD9822