AD9806KST Analog Devices Inc, AD9806KST Datasheet - Page 3

• Manufacturer Part Number: AD9806KST
• Description: IC CCD SIGNAL PROC 10BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9806KST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

CCD-MODE SPECIFICATIONS
Parameter
POWER CONSUMPTION
MAXIMUM CLOCK RATE
CDS
PGA
BLACK LEVEL CLAMP
SIGNAL-TO-NOISE RATIO
TIMING SPECIFICATIONS
NOTES
1
2
3
4
5
Specifications subject to change without notice.
Input signal characteristics defined as follows:
Use equations on page 8 to calculate gain.
SNR = 20 log
20 pF loading; timing shown in Figure 1.
Internal aperture delay for actual sampling edge.
V
V
V
Gain
Allowable CCD Reset Transient
Max Input Range before Saturation
Gain Control Resolution
Gain Range (See Figure 5a for Gain Curve)
Clamp Level (Selected through Serial Interface E-Reg)
Pipeline Delay
Internal Clock Delay
Inhibited Clock Period (t
Output Delay (t
Output Hold Time (t
ADCCLK, SHP, SHD Clock Period
ADCCLK High-Level/Low-Level
SHP, SHD Minimum Pulsewidth
SHP Rising Edge to SHD Rising Edge
TRANSIENT
500mV TYP
DD
DD
DD
Low Gain (Code 95)
Max Gain (1023)
CLP0 (E-Reg 00)
CLP1 (E-Reg 01)
CLP2 (E-Reg 10)
CLP3 (E-Reg 11)
RESET
= 2.7
= 3.0
= 3.3
BLACK PIXEL
10
200mV MAX
OPTICAL
(Full-Scale Voltage/RMS Output Noise).
OD
)
2
5
HOLD
(t
2
SIGNAL RANGE
ID
INHIBIT
)
)
1V MAX
INPUT
3
4
(@ Low PGA Gain)
)
1
1
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
Min
18
1000
–1
32
10
6
47
20
10
20
ADCCLK
= f
SHP
Typ
65
75
85
0
500
10
0
33
32
48
64
16
74
9
3
14.5
55.6
28
14
28
= f
SHD
= 18 MHz, unless otherwise noted.)
Max
+1
34
16
AD9806
Unit
mW
mW
mW
MHz
dB
mV
mV p-p
Bits
dB
dB
LSB
LSB
LSB
LSB
dB
Cycles
ns
ns
ns
ns
ns
ns
ns
ns