QT110-IS Atmel, QT110-IS Datasheet - Page 2

• Manufacturer Part Number: QT110-IS
• Description: SENSOR IC TOUCH/PROXMTY 1CH8SOIC
• Manufacturer: Atmel
• Series: QTouch™r
• Type: Capacitiver

Specifications of QT110-IS

• Rohs Status: RoHS non-compliant
• Touch Panel Interface: 1, 2-Wire
• Number Of Inputs/keys: 1 Key
• Resolution (bits): 14 b
• Data Interface: Serial
• Voltage Reference: Internal
• Voltage - Supply: 2.5V, 3.3V, 5V
• Current - Supply: 20µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Output Type: Logic
• Interface: 2-Wire
• Input Type: Logic
• Other names: 427-1002

1 - OVERVIEW
The QT110 is a digital burst mode charge-transfer (QT)
sensor designed specifically for touch controls; it includes all
hardware and signal processing functions necessary to
provide stable sensing under a wide variety of changing
conditions. Only a single low cost, non-critical capacitor is
required for operation.
Figure 1-1 shows the basic QT110 circuit using the device,
with a conventional output drive and power supply
connections. Figure 1-2 shows a second configuration using
a common power/signal rail which can be a long twisted pair
from a controller; this configuration uses the built-in pulse
mode to transmit output state to the host controller (QT110
only).
1.1 BASIC OPERATION
The QT110 employs short, ultra-low duty cycle bursts of
charge-transfer cycles to acquire its signal. Burst mode
permits power consumption in the low microamp range,
dramatically reduces RF emissions, lowers susceptibility to
EMI, and yet permits excellent response time. Internally the
signals are digitally processed to reject impulse noise, using
a
confirmations of a detection before the output is activated.
The QT switches and charge measurement hardware
functions are all internal to the QT110 (Figure 1-3). A 14-bit
single-slope switched capacitor ADC includes both the
required QT charge and transfer switches in a configuration
that provides direct ADC conversion. The ADC is designed to
dynamically optimize the QT burst length according to the
rate of charge buildup on Cs, which in turn depends on the
values of Cs, Cx, and Vdd. Vdd is used as the charge
reference voltage. Larger values of Cx cause the charge
transferred into Cs to rise more rapidly, reducing available
resolution; as a minimum resolution is required for proper
operation, this can result in dramatically reduced apparent
gain. Conversely, larger values of Cs reduce the rise of
differential voltage across it, increasing available resolution
by permitting longer QT bursts. The value of Cs can thus be
increased to allow larger values of Cx to be tolerated
(Figures 4-1, 4-2, 4-3 in Specifications, rear).
'consensus'
C M O S
GATE
Figure 1-2 2-wire operation, self-powered (QT110 only)
+3V
2 . 2k
filter
Tw ist e d
pa ir
which
requires
2
3
4
four
O UT
O PT 1
O PT 2
8
1
V dd
V s s
consecutive
S NS 2
S NS 1
G A IN
+
22 µF 10V AL
7
5
6
- 2 -
C
s
The IC is highly tolerant of changes in Cs since it computes
the threshold level ratiometrically with respect to absolute
load, and does so dynamically at all times.
Cs is thus non-critical; as it drifts with temperature, the
threshold algorithm compensates for the drift automatically.
A simple circuit variation is to replace Cs with a bare piezo
sounder (Section 2), which is merely another type of
capacitor, albeit with a large thermal drift coefficient. If C
is in the proper range, no other external component is
required. If C
with an inexpensive ceramic capacitor connected in parallel
with it. The QT110 drives a 4kHz signal across SNS1 and
SNS2 to make the piezo (if installed) sound a short tone for
75ms immediately after detection, to act as an audible
confirmation.
Option pins allow the selection or alteration of several
special features and sensitivity.
1.2 ELECTRODE DRIVE
The internal ADC treats Cs as a floating transfer capacitor;
as a direct result, the sense electrode can be connected to
either SNS1 or SNS2 with no performance difference. In both
cases the rule Cs >> Cx must be observed for proper
operation. The polarity of the charge buildup across Cs
during a burst is the same in either case.
10 nF
OU TP UT=D C
TIM EO UT= 10 S ecs
TOGG LE=OF F
GA IN= HIGH
E LE C T RO DE
S E NS IN G
Figure 1-1 Standard mode options
C
2
3
4
piezo
x
OU T
OP T1
OP T2
+2.5 to 5
is too small, it can simply be ‘topped up’
It is possible to connect separate Cx and
Cx’
simultaneously, although the result is no
different
connected together at SNS1 (or SNS2).
It is important to limit the amount of
stray capacitance on both terminals,
especially if the load Cx is already large,
for example by minimizing trace lengths
and widths so as not to exceed the Cx
load specification and to allow for a
larger sensing electrode size if so
desired.
The PCB traces,
components
contact with SNS1 and SNS2 will
become touch sensitive and should be
1
8
Vdd
Vss
S N S2
G A IN
S N S1
loads
7
5
6
than
to
associated
C
s
if
1 0nF
SNS1
the
wiring,
E LEC TRO DE
loads
with
and
S E NS ING
and any
or
C
SNS2
were
x
piezo
in