X96012V14IZ Intersil, X96012V14IZ Datasheet - Page 10

IC SENSOR CONDITION UNIV 14TSSOP

X96012V14IZ

Manufacturer Part Number
X96012V14IZ
Description
IC SENSOR CONDITION UNIV 14TSSOP
Manufacturer
Intersil
Type
Sensor Conditionerr
Datasheet

Specifications of X96012V14IZ

Input Type
Voltage
Output Type
Voltage
Interface
2-Wire
Current - Supply
15mA
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X96012V14IZ
Manufacturer:
INTERSIL
Quantity:
20 000
L1DA5 - L1DA0: LUT1 DIRECT ACCESS BITS
When bit L1DAS (bit 4 in Control register 5) is set to “1”,
LUT1 is addressed by these six bits, and it is not addressed
by the output of the on-chip A/D converter. When bit L1DAS
is set to “0”, these six bits are ignored by the X96012. See
Figure 10.
A value between 00h (00
these register bits, to select the corresponding row in LUT1.
The written value is added to the base address of LUT1
(90h).
Control Register 2
This register is accessed by performing a read or write
operation to address 82h of memory. This byte’s volatility is
determined by bit NV1234 in Control register 0.
L2DA5 - L2DA0: LUT2 DIRECT ACCESS BITS
When bit L2DAS (bit 6 in Control register 5) is set to “1”,
LUT2 is addressed by these six bits, and it is not addressed
by the output of the on-chip A/D converter. When bit L2DAS
is set to “0”, these six bits are ignored by the X96012. See
Figure 10.
A value between 00h (00
these register bits, to select the corresponding row in LUT2.
The written value is added to the base address of LUT2
(D0h).
Control Register 3
This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility is
determined by bit NV1234 in Control register 0.
D1DA7 - D1DA0: D/A 1 DIRECT ACCESS BITS
When bit D1DAS (bit 5 in Control register 5) is set to “1”, the
input to the D/A converter 1 is the content of bits D1DA7 -
D1DA0, and it is not a row of LUT1. When bit D1DAS is set
to “0” (default) these eight bits are ignored by the X96012.
See Figure 9.
10
10
) and 3Fh (63
) and 3Fh (63
10
10
10
) may be written to
) may be written to
X96012
February 20, 2008
FN8216.3

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