AD9895KBCZRL Analog Devices Inc, AD9895KBCZRL Datasheet - Page 9

• Manufacturer Part Number: AD9895KBCZRL
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9895KBCZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 30MSPS
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

SPECIFICATION DEFINITIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9891/AD9895 from a
true straight line. The point used as “zero scale” occurs 0.5 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 and 0.5 LSB beyond the last code transition. The
deviation is measured from the middle of each particular output
code to the true straight line. The error is then expressed as a
EQUIVALENT CIRCUITS
REV. A
THREE-
STATE
DATA
Figure 2. Digital Data Outputs
AVDD1
AVSS1
Figure 1. CCDIN
R
DVDD
DVSS
AVSS1
DRVDD
DRVSS
DOUT
–9–
percentage of the 2 V ADC full-scale signal. The input signal is
always appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques. The
standard deviation of the ADC output codes is calculated in LSB
and represents the rms noise level of the total signal chain at the
specified gain setting. The output noise can be converted to an
equivalent voltage, using the relationship 1 LSB = (ADC Full
Scale/2
AD9891, 1 LSB is 2 mV, while for the AD9895, 1 LSB is 0.5 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
RG, H1–H4
ENABLE
n
codes) when n is the bit resolution of the ADC. For the
Figure 4. H1–H4, RG Drivers
Figure 3. Digital Inputs
330
DVDD
DVSS
AD9891/AD9895
HVDD OR
RGVDD
HVSS OR
RGVSS
OUTPUT