AD9949KCPZ Analog Devices Inc, AD9949KCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9949KCPZ
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9949KCPZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 40
• Package Type: LFCSP EP
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9949
Table 8. AFE Register Map
Address
00
01
02
03
04
05
Table 9. Miscellaneous Register Map
Address
10
11
12
13
14
15
16
17
18
19
1A
Data Bit
Content
[11:0]
[9:0]
[7:0]
[11:0]
[17:0]
[17:0]
Data Bit
Content
[0]
[0]
[0]
[11:0]
[0]
[0]
[1:0]
[0]
[1:0]
[0]
[0]
Default Value
4
0
80
4
0
0
Default Value
0
0
0
0
0
0
0
0
0
1
0
Name
OPRMODE
VGAGAIN
CLAMP LEVEL
CTLMODE
PxGA GAIN01
PxGA GAIN23
Name
SW_RST
OUT_CONTROL
TGCORE_RSTB
UPDATE
PREVENTUPDATE
VDHDEDGE
FIELDVAL
HBLKRETIME
CLPBLKOUT
CLPBLKEN
TEST MODE
Rev. B | Page 14 of 36
Description
AFE Operation Modes. (See Table 14.)
VGA Gain.
Optical Black Clamp Level.
AFE Control Modes. (See Table 15.)
PxGA Gain Registers for Color 0 [8:0] and Color 1 [17:9].
PxGA Gain Registers for Color 2 [8:0] and Color 3 [17:9].
Description
Software Reset.
1 = Reset all registers to default, then self-clear back to 0.
Output Control.
0 = Make all dc outputs inactive.
Timing Core Reset Bar.
0 = Reset TG core.
1 = Resume operation.
Serial Update.
Sets the line (HD) within the field to update serial data.
Prevents the update of the VD updated registers.
1 = Prevent Update.
VD/HD Active Edge.
0 = Falling Edge Triggered.
1 = Rising Edge Triggered.
Field Value Sync.
0 = Next Field 0.
1 = Next Field 1.
2/3 = Next Field 2.
Retime HBLK to Internal H1 Clock.
Preferred setting is 1. Setting to 1 adds one cycle delay to HBLK
toggle positions.
CLP/BLK Pin Output Select.
0 = CLPOB.
1 = PBLK.
2 = HBLK.
3 = Low.
Enable CLP/BLK Output.
1 = Enable.
Internal Test Mode.
Should always be set high.