AD22057R Analog Devices Inc, AD22057R Datasheet - Page 7

• Manufacturer Part Number: AD22057R
• Description: IC AMP DIFF SNGL-SUP 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Sensor Interfacer

Specifications of AD22057R

• Rohs Status: RoHS non-compliant
• Input Type: Voltage
• Output Type: Analog
• Interface: Differential
• Current - Supply: 200µA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)

APPLICATION HINTS
Frequency Compensation
As are all closed-loop op amp circuits, the AD22057 is sensitive
to capacitive loading at its output. However, the AD22057 is
sensitive at higher output voltages due to nonlinear effects in
the rail-to-rail design of the buffer amplifier (A2). In this
amplifier the output stage gain increases with increasing output
voltage. This behavior does not affect dc parameters such as
gain accuracy or linearity; however, it can compromise ac sta-
bility. When operating from a power supply of 5 V or less (and,
therefore, V
loads up to 25 pF with no external components. When operat-
ing at higher supply voltages (which are associated with higher
output voltages) and/or driving larger capacitive loads, an exter-
nal compensation network should be used. Figure 14 shows an
R-C “snubber” circuit loading the output of the AD22057.
This combination, in conjunction with the internal 20 k resis-
tance, forms a lag network. This network attenuates the open-
loop gain of the amplifier at higher frequencies. The ratio of
R
frequency attenuation seen by the op amp. If R
1/20th of the total load resistance ( 20 k R
attenuation is obtained at higher frequencies. The capacitor
(C
network. It should be set to form a 5 s time constant with the
resistor (R
R
Ten percent tolerance on these components is acceptable.
Alternatively, the signal may be taken from the midpoint of
R
CMOS analog-to-digital converters. For more information see
the section Driving Charged Redistributed A/D Converters.
Note that when implementing this network large signal re-
sponse is compromised. This occurs because there is no active
pull-down and the lag capacitor must discharge through the
internal feedback resistor (20 k ) giving a fairly long-time
constant. For example if C
negative slew characteristic is a decaying exponential with a
time constant of 200 s.
Driving Charge Redistribution A/D Converters
When driving CMOS ADCs, such as those embedded in popu-
lar microcontrollers, the charge injection ( Q) can cause a
significant deflection in the AD22057 output voltage. Though
generally of short duration, this deflection may persist until
after the sample period of the ADC has expired. It is due to the
relatively high open-loop output impedance of the AD22057.
The effect can be significantly reduced by including the same
R-C network recommended for improving stability (see Fre-
quency Compensation section). The large capacitor in the lag
REV. A
LAG
LAG
LAG
LAG
Table I. Compensation Components vs. External Load
Resistor
–C
to the load seen by the AD22057 determines the high
and C
) is used to control the frequency of the compensation
LAG
R
>100 k
>
>
>
>
>
LAG
L
. This output is particularly useful when driving
50 k
20 k
10 k
5 k
2 k
OUT
LAG
). Table I shows the recommended values of
for various values of external load resistor R
< 5 V), the AD22057 can drive capacitive
LAG
R
470
390
270
200
100
47
LAG
= 0.01 F, the large signal
C
0.01 F
0.01 F
0.047 F
0.047 F
0.1 F
0.22 F
L
), then 26 dB of
LAG
LAG
is made
L
.
–7–
network helps to absorb the additional charge, effectively lower-
ing the high frequency output impedance of the AD22057. For
these applications the output signal should be taken from the
midpoint of the R
Since the perturbations from the analog-to-digital converter are
small, the output of the AD22057 will appear to be a low
impedance. The transient response will, therefore, have a
time constant governed by the product of the two lag compo-
nents, C
time constant is programmed at approximately 10 s. There-
fore, if samples are taken at several tens of microseconds or more,
there will be negligible “stacking up” of the charge injections.
UNDERSTANDING THE AD22057
Figure 16 shows the main elements of the AD22057. The signal
inputs at Pins 1 and 8 are first applied to dual resistive attenua-
tors R1 through R4, whose purpose is to reduce the common-
mode voltage at the input to the preamplifier. The attenuated
signal is then applied to a feedback amplifier based on the very
low drift op amp, A1. The differential voltage across the inputs
is accurately amplified in the presence of common-mode volt-
ages of many times the supply voltage. The overall common-
mode response is minimized by precise laser trimming of R3
and R4, giving the AD22057 a common-mode rejection ratio
(CMRR) of at least 80 dB (10,000:1).
The common-mode range of A1 extends from slightly below
ground to 1 V below +V
–40 C). Since an attenuation ratio of about 6 is used, the input
common-mode range is –1 V to +24 V using a +5 V supply.
Small filter capacitors C1 and C2 are included to minimize the
effects of spurious RF signals at the inputs, which might cause
dc errors due to the rectification effects at the input to A1. At
high frequencies, even a small imbalance in these components
would seriously degrade the CMRR, so a special high frequency
trim is also carried out during manufacture.
Figure 15. Recommended Circuit for Driving CMOS A/D
Converters
Figure 14. Using an R-C Network for Compensation
LAG
+V
S
R
LAG
LAG
AD22057
. For the values shown in Figure 15, this
+V
10k
10k
–C
A2
AD22057
S
10k
10k
LAG
A2
S
(at the minimum temperature of
combination as shown in Figure 15.
1k
0.01 F
R
C
LAG
LAG
AD22057
IN
PROCESSOR
R
LOAD
L
A/D
C
L