BU21010MUV-E2 Rohm Semiconductor, BU21010MUV-E2 Datasheet - Page 8

• Manufacturer Part Number: BU21010MUV-E2
• Description: IC CTLR CAP SENSOR 8CH 16VQFN
• Manufacturer: Rohm Semiconductor
• Type: Capacitive Sensor Controllerr

Specifications of BU21010MUV-E2

• Input Type: Logic
• Output Type: Logic
• Interface: 2-Wire Serial
• Current - Supply: 300µA
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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BU21010MUV
www.rohm.com
【62h : Gesture Direction Judgment】
【E2h : Gesture Clear】
【E3h : Gesture Function Setting】
Initial val.
Initial val.
Initial val.
Name:
Address:
Description:
Name:
Address:
Description:
Name:
Address:
Description:
The condition and the direction of detection that can be detected in each mode are as follows.
R/W
R/W
R/W
E2h
E3h
62h
DIR_A : gesture direction A
0xE3(GES_CTL) reference
DIR_B : gesture direction B
0xE3(GES_CTL) reference
EN : enable
These are the enable bits. One is provided for each of the 4 sense inputs used for gesture. EN[0] is for SN0, EN[1] is for
SN2, EN[2] is for SN4 and EN[3] is for SN6. 1 is to enable and 0 is for disable.
MODE : mode
0 : Requires all sensors to be present in the sequence before the gesture is recognized.（All detection mode）
1 : Allows one or more of the keys to be missed in the sequence.（Verbose mode）
All detection
Verbose
mode
CLR
This register when written to clears GES_VEL and GES_DIR.
It is cleared by one, and it returns to 0 by the automatic operation.
This register controls what key-press sequence is recognized as a gesture.
Only 4 channels may be used - SIN0, SIN2, SIN4, and SIN6.
Bit7
Bit7
Bit7
GES_DIR
62h
GES_CLR
E2h
GES_CTL
E3h
W
Gesture direction judgment
0
-
-
-
-
-
-
Bit6
Bit6
Bit6
-
-
-
-
-
-
-
-
-
MODE
0
1
Bit5
Bit5
Bit5
-
-
-
-
-
-
-
-
-
Direction（GES_DIR）
MODE
DIR_A
DIR_B
DIR_A
DIR_B
Bit4
Bit4
Bit4
W
8/14
1
-
-
-
-
-
-
EN[3]
Bit3
Bit3
Bit3
W
1
-
-
-
-
-
-
1)SIN0→SIN2→SIN4→SIN6
1)SIN6→SIN4→SIN2→SIN0
1)SIN0→SIN2→SIN4
2)SIN0→SIN2→
3)
4)SIN0→
5)
1)SIN6→SIN4→SIN2
2)SIN6→SIN4→
3)
4)SIN6→
5)
EN[2]
Bit2
Bit2
Bit2
W
1
SIN2→SIN4→SIN6
SIN2→
SIN4→SIN2→SIN0
SIN4→
-
-
-
-
-
-
Detected
SIN4
SIN2
DIR_B
EN[1]
Bit1
Bit1
Bit1
W
R
0
1
-
-
-
SIN6
SIN0
SIN6
SIN0
2009.04 - Rev.B
Technical Note
DIR_A
EN[0]
Bit0
Bit0
Bit0
W
R
0
1
-
-
-