QT60240-ISG Atmel, QT60240-ISG Datasheet
QT60240-ISG
Specifications of QT60240-ISG
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QT60240-ISG Summary of contents
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... Orgacon is a registered tra demark of Agfa-Gevaert N AND EY AVAILABLE OPTIONS Part Number Keys QT60160-ISG 16 QT60240-ISG 24 QT60160, QT60240 ™ ATRIX OUCH ENSOR M_SYNC 1 CHANGE 2 QT60240 VSS 3 QT60160 VDD 4 VSS 5 MLF-32 VDD † ink on film - + - +85 C Copyright © 2006 QRG Ltd QT60240-ISG R8.06/0906 Y1B 23 Y0B VSS 20 VDD VDD ...
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... QT60240-ISG R8.06/0906 ...
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... After the burst completes, the device clamps the Y line to ground causing the opposite terminal to go negative. The charge then measured using an external resistor to ramp the negative terminal upwards until a zero crossing is achieved. The time required to zero cross becomes the measurement result. 3 Table 2.1 Key Numbers QT60240-ISG R8.06/0906 ...
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... Rs. However, long adjacent runs of X and Y lines can also artificially boost the signal values, and induce signal saturation; this avoided. The X-to-Y coupling should come mostly from intra-key electrode coupling, not from stray X-to-Y trace coupling. 4 QT60240-ISG R8.06/0906 ...
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... X line(s) should be reduced (by a layout change, for example by reducing X line exposure to nearby ground planes or traces), or, the Rx resistor needs to be reduced in value (or a combination of both approaches QT60240-ISG R8.06/0906 ...
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... Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A regulator can be shared among two or more QT devices on one board. One such regulator known to work well with QT chips is the S-817 series from Seiko Instruments (Seiko Instruments - www.sii-ic.com). 6 QT60240-ISG R8.06/0906 ...
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... Key touch activity will prevent the part from sleeping. The part will not sleep if any touch events were detected at any key in the most recent scan of the key matrix. 7 QT60240-ISG R8.06/0906 ...
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... If Unused, Connect To... Vdd Leave open - - - - Leave open Leave open Leave open - Leave open Leave open Leave open Leave open Leave open Leave open Leave open - - - - - Leave open Leave open Leave open - - - Leave open or Vdd Leave open Leave open Leave open QT60240-ISG R8.06/0906 ...
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... QT60160 10K 10K 9 *RX7 *RX6 1K *RX5 1K 1K *RX3 *RX2 1K *RX1 optional - for emission suppression ** optional - for RF susceptibility improvement **RY0 CS0 4.7nF **RY1 CS1 4.7nF **RY2 CS2 4.7nF Note: Leave YnA, YnB unconnected if not used RS2 RS1 RS0 QT60240-ISG R8.06/0906 *RX4 1K *RX0 ...
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... Figure 3.1 Shift Register Output 74HC595 27 SDA DS 28 SH_CP SCL 9 Latch ST_CP 74HC595 DS SH_CP ST_CP 74HC595 DS SH_CP ST_CP Port 2 C communications, in slave mode only operating parameters are as follows: Max Data Transfer: 100KHz Address: 7-bit Outputs, keys / Outputs, keys / Outputs, keys /Q7 QT60240-ISG R8.06/0906 ...
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... The configuration is set in the Setups block (Section 6.13 key-by-key basis. Figure 3.2 Shift Register Cycle Key 2 Key 21 Key 22 Key 23 Key 0 Key 3 Key 4 t SCL SCH SDA-SCL QT60240-ISG R8.06/0906 Key 23 t LATCH ...
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... Key S Start condition SLA+W Slave address plus write bit A Acknowledge bit Target memory address within MemAddress device Data Data from device P Stop condition SLA+R Slave address plus read bit Not Acknowledge bit/indicates /A last byte transmission QT60240-ISG R8.06/0906 Device to Host SLA+R A Data ...
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... Addresses 131 to 252 provide read/write access to the setups. Details of different setups can be found in Section 6, page 17. When the host is writing a new setup block the values are being recorded into EEPROM as they arrive from the host communication sequence. Reading this QT60240-ISG R8.06/0906 ...
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... Block Incorrect Setup Data Correct Setup Block 'CHANGE' output set Host main Process Keys OK Recalibrate All Send 0x55 to Addr 125 Stuck Key Detected 14 Recalibrate All Send Correct Send 0x55 to Setup Block Addr 125 Legend Internal Host Processes Comms with QT QT60240-ISG R8.06/0906 ...
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... SDA line low during the ninth SCL cycle. If the Data Stable Receiver leaves the SDA line high, a NACK is signaled. 15 Figure 5.3 START and STOP Conditions SDA SCL START Figure 5.4 Address Packet Format Addr MSB Addr LSB START QT60240-ISG R8.06/0906 STOP R/W ACK 8 9 ...
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... SLA +R/W and the STOP. Figure 5.5 Data Packet Format Data MSB 1 2 Data Byte Figure 5.6 Packet Transmission Addr LSB R/W ACK Data MSB Data LSB ACK STOP, or Next Data Byte Data LSB ACK Data Byte QT60240-ISG R8.06/0906 9 STOP ...
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... The drift compensation mechanism can be asymmetric; the drift-compensation can be made to occur in one direction faster than it does in the other simply by changing the NDRIFT and PDRIFT Setup parameters. This can be done on a per-key basis. Figure 6.1 Thresholds and Drift Compensation Hysteresis Threshold Output 17 Reference Signal QT60240-ISG R8.06/0906 ...
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... This condition can occur if there is positive drift but insufficient positive drift compensation , or, if the reference moved negative due to a NRD auto-recalibration, and thereafter the signal rapidly returned to normal (positive excursion). 18 QT60240-ISG R8.06/0906 ( seconds) 20 (10 seconds) 0..254 (∞ ...
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... The sync signal drive should be a buffered logic signal, or perhaps a diode-clamped signal, but never a raw AC signal from the mains. The device will synchronize to the falling edge. 19 QT60240-ISG R8.06/0906 0 (Off) 0 (Off) ...
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... DHT can be configured to a value of between 100ms and 25.5s, in increments of 100ms. Setting this parameter to 0 will disable this feature and the drift compensation on any key will not be dependent on the state of other keys. DHT default value: 10 (1s) DHT range: 0...255 (Off, 100ms...25.5s) 20 QT60240-ISG R8.06/0906 25 (2.5s) 1...255 (100ms...25.5s) ...
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... Bits 2,1,0 = Sleep Duration, 8 values via LUT, default = 125ms MSYNC = 0 Bits 6 = Mains sync, negative edge enabled, default = off 1...255 Range is in 100ms increments 100ms. Default = 2.5s illegal to use 0...255 Range is in 100ms increments disable 100ms, default = 1s 21 Description Page QT60240-ISG R8.06/0906 ...
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... SLEEP AKS SSYNC MSYNC ms (Page 19) (Page 19) (Page 20) (Page 19) Per key Per key Global Global 16 - Off - - Off - -125- 250 500 1,000 2,000 QT60240-ISG R8.06/0906 AWAKE DHT secs secs (Page 20) (Page 20) Global Global - Off - unused Off On 0.1...25.5s 0.1...25.5s Default= Default= 2.5s 1s ...
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... Min Typ Max 270 380 490 600 155 ± + +125 Units Notes Vdd = 1.8V mA Vdd = 3.3V Vdd = 5.0V Vdd = 1.8V µA Vdd = 3.3V Vdd = 5.0V V 1.8V <Vdd <5V V 1.8V <Vdd < µA bits k✡ Units Notes µ kHz % QT60240-ISG R8.06/0906 ...
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... QT60240-ISG R8.06/0906 x KE) BS ...
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... Moisture Sensitivity Level (MSL) MSL Rating MSL3 Nominal Maximum 0.90 1.00 0.02 0.05 0.65 1.00 0.20 REF 5.00 BSC 5.00 BSC 0.23 0. 0.40 0.50 3.10 3.25 3.10 3.25 0.50 BSC Keys Marking 16 6160 24 6240 Peak Body Temperature Specifications O 260 C IPC/JEDEC J-STD-020C QT60240-ISG R8.06/0906 e A3 ...
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This device is covered under one or more United States and corresponding international patents. QRG patent numbers can be found online at www.qprox.com. Numerous further patents are pending, which may apply to this device or the applications thereof. The ...