MPR084EJ Freescale Semiconductor, MPR084EJ Datasheet - Page 6

IC CTLR TOUCH SENSR PROX 16TSSOP

MPR084EJ

Manufacturer Part Number
MPR084EJ
Description
IC CTLR TOUCH SENSR PROX 16TSSOP
Manufacturer
Freescale Semiconductor
Type
Capacitiver
Datasheet

Specifications of MPR084EJ

Number Of Inputs/keys
8 Key
Data Interface
I²C, Serial
Voltage - Supply
1.8 V ~ 3.6 V
Current - Supply
1.62mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Output Type
Voltage
Interface
I²C
Input Type
Logic
Supply Voltage
3.3 V
Dimensions
5 mm L x 4.4 mm W x 1.05 mm H
For Use With
KITMPR084EVM - KIT EVAL 8-PAD TOUCH MPR084
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPR084EJ
Manufacturer:
FRE/MOT
Quantity:
20 000
MPR084
6
2.3.2
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START
(S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the
slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another
transmission.
2.3.3
One data bit is transferred during each clock pulse
2.3.4
The acknowledge bit is a clocked 9
byte transferred effectively requires 9 bits. The master generates the 9
the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is
transmitting to the MPR084, the MPR084 generates the acknowledge bit because the MPR084 is the recipient. When the
MPR084 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.
BY TRANSMITTER
Start and Stop Conditions
Bit Transfer
Acknowledge
BY RECEIVER
SDA
SCL
SDA
SCL
SDA
SDA
SCL
CONDITION
START
CONDITION
S
START
S
DATA LINE STABLE
th
DATA VALID
bit
(Figure
Figure 6. Start and Stop Conditions
1
8) which the recipient uses to handshake receipt of each byte of data. Thus each
(Figure
Figure 8. Acknowledge
Figure 7. Bit Transfer
DATA ALLOWED
7). The data on SDA must remain stable while SCL is high.
CHANGE OF
2
th
clock pulse, and the recipient pulls down SDA during
ACKNOWLEDGEMENT
CLOCK PULSE FOR
8
CONDITION
Freescale Semiconductor
STOP
P
9
Sensors

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