SI2493-C-GT Silicon Laboratories Inc, SI2493-C-GT Datasheet - Page 171

• Manufacturer Part Number: SI2493-C-GT
• Description: IC ISOMODEM SYSTEM-SIDE 24TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2493-C-GT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, V.34, V.90, V.92, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Layout Guidelines
The key to a good layout is the proper placement of
components. It is best to copy the placement shown on
our evaluation boards (see the reference layout
included in this appendix). Alternatively, perform the
following steps, referring to the schematics.
1. All traces, open pad sites, and vias connected to the
2. The isolation capacitors, C1, C2, C8, and C9, are the
3. Place and group the following components: U1, U3,
4. Place and group the following components around
5. Place and group the following components around
following components are considered to be in the
DAA section and must be physically separated from
non-DAA circuits by 5 mm to achieve the best
possible surge performance: R1, R2, R4, R5, R6,
R7, R8, R10, R15, R16, R18, R19, R20, R21, U3,
Z1, D1, FB1, FB2, RJ11, Q1, Q2, Q3, C3, C4, C5,
C8, C9, C11, RV1, C1 pin 2 only, C2 pin 2 only, C8
pin 2 only, and C9 pin 2 only.
only components permitted to straddle between the
DAA section and non-DAA section components and
traces. This means that for each of these capacitors,
one of the terminals is on the DAA-side, and the
other is not. Maximize the spacing between the
terminals (between pin 1 and pin 2) of each of these
capacitors.
R12, R13, C1, and C2.
U3: C4, R18, R19, R20, R21, C5, C11, R7, and R8.
These components should form the critical “inner
circle” of components around U2. Refer to Figure 38
on page 173 for a sample placement.
the RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and
C9.
a.U1 and U3 are placed so that the right side of U1
b.C1 and C2 should be placed directly between U1
c.Keep R12 and R13 close to U1.
d.Place U1, U3, C1, and C2 to realize the
e.Place C1 and C2 so that traces connected to U3
a.Use 20 mil width traces on this grouping to
faces the left side of U3.
and U3.
recommended minimum creepage spacing for
the target application.
pin 1 (C1B) and U3 pin 2 (C2B) are physically
separated from traces connected to:
minimize impedance.
iC8, R15, FB1
ii.C9, R16, FB2
Rev. 0.9
6. After the previous step, there should be some space
7. The epad of U3 (pin 9) is also known as IGND. This
8. The traces from R7 to FB1 and from R8 to FB2
9. Minimize all traces associated with Y1, C40, and
10.Decoupling capacitors (0.22 µF and 0.1 µF)
between the grouping around U3 and the grouping
of components around the RJ11 jack. Place the rest
of the components in this area, given the following
guidelines:
is the ground return path for many of the discrete
components and requires special mention.
should be well matched. This can be achieved by
routing these traces next to each other if possible.
Ensure that these traces are not routed close to the
traces connected to C1 or C2.
C41, and allow NO other traces to be routed through
this circuitry.
connected to VA, VD must be placed next to those
pins. Traces of these decoupling capacitors back to
the Si2401 GND pin should be direct and short.
b.Place C8 and C9 close to the RJ11 jack,
c.The trace from C8 to GND and from C9 to GND
a.Space U2, Q1, Q2, Q3, R1, R2, and R10 away
b.Place C3 next to D1.
c.Make the size of the Q1, Q2, and Q3 collector
a.Route traces associated with IGND using 20 mil
b.The area underneath U3 should be ground-filled
c.C5, IGND return path should be direct.
d.The IGND plane must not extend past the diode
recognizing that a GND trace will be routed
between C8 and C9, back to the Si24xx GND pin,
through a minimum 20 mil wide trace. The GND
trace from C8 and C9 must be isolated from the
rest of the Si3008 traces.
must be short and equidistant.
from each other for optimal thermal performance.
R1 and R2 can each dissipate nearly 0.75 W
under worst-case conditions.
pads each sufficiently large to safely dissipate
0.15 W under worst-case conditions. See the
transistor data sheet for thermal resistance and
maximum operating temperature information.
Implement collector pads on both the compound
and solder side and use vias between them to
improve heat transfer for best performance.
traces.
and connected to IGND (U3 pin 9). Ground fill
both the solder side and the component side and
stitch together using vias.
bridge.
AN93
171