SI2415-C-GT Silicon Laboratories Inc, SI2415-C-GT Datasheet - Page 53

• Manufacturer Part Number: SI2415-C-GT
• Description: IC ISOMODEM W/DAA 24TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2415-C-GT

• Mfg Application Notes: SI2493/57/34/15/04, Appl Note AN93
• Data Format: V.21, V.22, V.23, V.29, V.32, Bell 103, Bell 212A
• Baud Rates: 14.4k
• Interface: Parallel, UART
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

U68 ITC2
Reset settings = 0x0000
Name
15:3
Type
Bit
Bit
Bit
2
1
0
1
0
Reserved Do not modify.
D15 D14 D13 D12 D11 D10
Name
Name
ROV
BTE
BTD
RZ
RT
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesize ringer impedance. C15, R14, Z2, and Z3 must not be installed when setting this
bit. See the “Ringer Impedance” section in “AN93: Modem Designer’s Guide”.
Ringer Threshold Select.
Used to satisfy country requirements on ring detection. Signals below the lower level does not
generate a ring detection; signals above the upper level are guaranteed to generate a ring
detection.
0 = 11 to 22 V
1 = 17 to 33 V
Billing Tone Protect Enable.
0 = Disabled.
1 = Enabled.
When set, the DAA responds automatically to a collapse of the line-derived power supply dur-
ing a billing tone event. When off-hook, if BTE = 1 and BTD goes high, the dc termination is
released (800 Ω presented to line). If BTE and RIM (U70, bit 9) are set, an RI (U70, bit 1)
interrupt also occurs when BTD goes high.
Receive Overload.
The bit is set when the receive input (i.e., receive pin goes below ground) has an excessive
input level. This bit is cleared by writing a 0 to this location.
0 = Normal receive input level.
1 = Excessive receive input level.
Billing Tone Detected.
This bit is set if a billing tone is detected. This bit is cleared by writing a 0 to this location.
0 = No billing tone.
1 = Billing tone detected.
rms
rms
.
.
D9
Rev. 1.1
D8
D7
Function
Function
D6
D5
Si2457/34/15/04
D4
D3
BTE ROV BTD
R/W R/W R/W
D2
D1
D0
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