SI3012-KS Silicon Laboratories Inc, SI3012-KS Datasheet - Page 32

• Manufacturer Part Number: SI3012-KS
• Description: IC ISOMODEM SYSTEM-SIDE 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3012-KS

• Data Format: V.90
• Interface: Serial
• Voltage - Supply: 3.3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Baud Rates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3038
The AC-link protocol provides for a special 16-bit time
slot (Slot 0) wherein each bit conveys a valid tag for its
corresponding time slot within the current audio frame.
A 1 in a given bit position of slot 0 indicates that the
corresponding time slot within the current audio frame
has been assigned to a data stream and contains valid
data. If a slot is tagged invalid, it is the responsibility of
the data source (the Si3024 for the input stream, the
AC’97 controller for the output stream) to populate all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs
at the beginning of each audio frame. The portion of the
audio frame where SYNC is high is called the Tag
Phase. The remainder of the audio frame where SYNC
is low is called the data phase. See Figure 28.
Additionally, for power savings, all clock, sync, and data
signals can be halted. The Si3038 chipset maintains its
register contents intact when entering a power-savings
mode.
AC-Link Audio Output Frame (SDATA_OUT)
The audio output frame data streams correspond to the
multiplexed bundles of all digital output data targeting
the Si3038’s DAC inputs and control registers. Each
audio output frame supports up to 12 20-bit outgoing
data time slots. Slot 0 is a special reserved time slot
containing
infrastructure.
Within slot 0, the first bit is a global bit (SDATA_OUT
slot 0, bit 15) which flags the validity for the entire audio
frame. If the Valid Frame bit is a 1, the current audio
frame contains at least one slot time of valid data. The
next 12 bit positions sampled by the Si3024 indicate
which of the corresponding 12 time slots contain valid
data. In this way, data streams of differing sample rates
can be transmitted across AC-link at its fixed 48-kHz
audio frame rate. Figure 29 illustrates the time slot-
based AC-link protocol.
A new audio output frame begins with a low to high
transition of SYNC. SYNC is synchronous to the rising
32
SDATA_OUT
BIT_CLK
SYNC
End of previous
Audio Frame
16
bits
Frame
Valid
12.228 MHz
slot(1)
("1" = Time slot contains valid PCM data)
used
slot(2)
Tag Phase
81.4 nS
Time Slot "Valid"
for
Figure 29. AC-Link Audio Output Frame
Bits
slot(12)
AC-link
"0"
"0"
protocol
"0"
Rev. 2.01
19
Slot 1
edge of BIT_CLK. On the immediately following falling
edge of BIT_CLK, the Si3024 samples the assertion of
SYNC. This falling edge marks the time when both
sides of AC-link are aware of the start of a new audio
frame. On the next rising of BIT_CLK, the AC’97
controller transitions SDATA_OUT into the first bit
position of slot 0 (Valid Frame bit). Each new bit position
is presented to AC-link on a rising edge of BIT_CLK,
and subsequently sampled by the Si3024 on the
following falling edge of BIT_CLK. This sequence
ensures that data transitions and subsequent sample
points for both incoming and outgoing data streams are
time aligned. See Figure 30.
SDATA_OUT’s composite stream is MSB justified (MSB
first) with all non-valid slots’ bit positions padded with 0s
by the AC’97 controller.
In the event that there are less than 20 valid bits within
an assigned and valid time slot, the AC’97 controller
always pads all trailing non-valid bit positions of the 20-
bit slot with 0s.
Variable Sample Rate Signaling Protocol
For variable sample rate output, the codec examines its
sample rate control registers, the state of its FIFOs, and
SDATA_OUT
Figure 30. Start of an Audio Output Frame
(48 KHz)
0
20.8
BIT_CLK
µ
S
19
SYNC
Slot 2
Data Phase
0
End of previous
Audio Frame
19
AC '97 samples SNYC assertion here
Slot 3
Frame
Valid
AC '97 samples SDATA_O UT bit of frame here
0
slot (1) slot (2)
19
Slot 12
0