CP82C55A Intersil, CP82C55A Datasheet - Page 4

• Manufacturer Part Number: CP82C55A
• Description: IC I/O EXPANDER 24B 40DIP
• Manufacturer: Intersil

Specifications of CP82C55A

• Interface: Programmable
• Number Of I /o: 24
• Interrupt Output: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Chip Configuration: 8 Bit
• Bus Frequency: 8MHz
• No. Of I/o's: 24
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Function: Programmable I/O
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency - Clock: -

Functional Description
Data Bus Buffer
This three-state bidirectional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status
information are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A “low” on this input pin enables the
communication between the 82C55A and the CPU.
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400μA.
A1
X
X
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
X
X
RD
X
0
0
0
0
1
1
1
1
1
82C55A BASIC OPERATION
WR
1
1
1
1
0
0
0
0
X
1
CS
0
0
0
0
0
0
0
0
1
0
4
Port A → Data Bus
Port B → Data Bus
Port C → Data Bus
Control Word → Data Bus
Data Bus → Port A
Data Bus → Port B
Data Bus → Port C
Data Bus → Control
Data Bus → Three-State
Data Bus → Three-State
OUTPUT OPERATION
DISABLE FUNCTION
INPUT OPERATION
(WRITE)
(READ)
82C55A
Group A and Group B Controls
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a
control word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that
initializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or “personality” to further enhance the power and flexibility of
the 82C55A.
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
RESET
D7-D0
SUPPLIES
BIDIRECTIONAL
WR
RD
POWER
A1
A0
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
DATA BUS
CS
CONTROL
WRITE
LOGIC
BUFFER
READ
DATA
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
BUS
+5V
GND
CONTROL
CONTROL
GROUP A
GROUP B
INTERNAL
DATA BUS
8-BIT
GROUP A
GROUP B
GROUP B
GROUP A
PORT A
PORT C
PORT B
PORT C
LOWER
UPPER
(8)
(4)
(8)
(4)
November 16, 2006
FN2969.10
PA7-
PC7-
PC3-
PB7-
PA0
PC4
PC0
PB0
I/O
I/O
I/O
I/O