MF8CCN National Semiconductor, MF8CCN Datasheet - Page 4

• Manufacturer Part Number: MF8CCN
• Description: IC LOWPASS FILTER 4TH ORD SW CAP
• Manufacturer: National Semiconductor

Specifications of MF8CCN

• Filter Type: Bandpass
• Frequency - Cutoff Or Center: 20kHz
• Number Of Filters: 2
• Max-order: 4th
• Voltage - Supply: 9 V ~ 14 V, ±4.5 V ~ 7 V
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *MF8CCN

Note 7 If it is possible for a signal output (pin 6 14 or 15) to be shorted to V
Note 8 If V
typical V
Note 9 Typicals are at 25 C and represent the most likely parametric norm
Note 10 Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11 Design Limits are guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels
Note 12 These logic levels have been referenced to V
Pin Descriptions
Q Logic Inputs
A B C D E
(3 2 1 18 17)
AGND (4)
V
V
F1 IN (16)
F2 IN (5)
F1 OUT (15)
F2 OUT (6)
A IN (13)
A OUT (14)
50 100 (10)
TTL CLK (7)
CMOS CLK (8)
b
a
(11)
(12)
T
a
b
e
is anything other than 0V then the value of V
0 7 (10V)
These inputs program the Qs of the two
2nd-order bandpass filter stages Logic
‘‘1’’ is V
This is the analog and digital ground pin
and should be connected to the system
ground for split supply operation or bi-
ased to mid-supply for single supply op-
eration For best filter performance the
ground line should be ‘‘clean’’
These are the positive and negative
power supply inputs Decoupling the
power supply pins with 0 1
capacitors is highly recommended
These are the inputs to the bandpass fil-
ter stages To minimize gain error the
source impedance should be less than 2
k
to AGND
These are the outputs of the bandpass
filter stages
This is the inverting input to the uncom-
mitted operational amplifier The non-in-
verting input is internally connected to
AGND
This is the output of the uncommitted
operational amplifier
This pin sets the ratio of the clock fre-
quency to the bandpass center frequen-
cy Connecting this pin to V
ratio to 100 1 Connecting it to V
the ratio to 50 1
This is the TTL-level clock input pin
There are two logic threshold levels so
the MF8 can be operated on either sin-
gle-ended or split supplies with the logic
input referred to either V
When this pin is not used (or when
CMOS logic levels are used) it should
be connected to either V
This pin is the input to a CMOS Schmitt
inverter Clock signals with CMOS logic
levels may be applied to this input If the
TTL input is used this pin should be con-
nected to V
a
(
b
Input signals should be referenced
5V)
a
e a
and logic ‘‘0’’ is V
b
2V
b
a
b
The logic levels will shift accordingly for split supplies
b
or V
b
a
should be added to the values given in the table For example for V
F or larger
or AGND
sets the
b
b
sets
a
4
V
b
ures 2a 2b and 2c The two second-order filter sections can
RC (9)
1 0 Application Information
1 1 INTRODUCTION
A simplified block diagram for the MF8 is shown in Figure 1
The analog signal path components are two identical 2nd-
order bandpass filters and an operational amplifier Each
filter has a fixed voltage gain of 2 The filters’ cutoff frequen-
cy is proportional to the clock frequency which may be ap-
plied to the chip from an external source or generated inter-
nally with the aid of an external resistor and capacitor The
proportionality constant f
100 depending on the logic level on pin 10 The ‘‘Q’’ of the
two filters can have any of 31 values ranging from 0 5 to 90
and is set by the logic levels on pins 1 2 3 17 and 18
Table I shows the available values of Q and the logic levels
required to obtain them The operational amplifier’s non-in-
verting input is internally grounded so it may be used only
for inverting applications
The components in the analog signal path can be intercon-
nected in several ways three of which are illustrated in Fig-
be used as separate filters whose center frequencies track
very closely as in Figure 2a Each filter section has a high
input impedance and low output impedance The op amp
may be used for gain scaling or other inverting functions If
sharper cutoff slopes are desired the two filter sections
may be cascaded as in Figure 2b Again the op amp is
uncommitted The circuit in Figure 2c uses both filter sec-
tions with the op amp and three resistors to build a ‘‘multiple
feedback loop’’ filter This configuration offers the greatest
flexibility for fourth-order bandpass designs Virtually any
fourth-order all pole response shape (Butterworth Cheby-
shev) can be obtained with a wide range of bandwidths
simply by proper choice of resistor values and Q The three
connection schemes in Figure 2 will be discussed in more
detail in Sections 1 4 and 1 5
or ground add a series resistor to limit output current
This pin allows the MF8 to generate its
own clock signal To do this connect an
external resistor between the RC pin and
the CMOS Clock input and an external
capacitor from the CMOS Clock input to
AGND The TTL Clock input should be
connected to V
is driven from an external clock the RC
pin should be left open
CLK
f
0
can be set to either 50 or
a
b
e a
or V
5V and V
a
When the MF8
b
e b
5V the