MC44725AVFU Freescale Semiconductor, MC44725AVFU Datasheet
MC44725AVFU
Specifications of MC44725AVFU
Related parts for MC44725AVFU
MC44725AVFU Summary of contents
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Advanced Information Advanced Digital Video Encoder Y/Cb/Cr R/G/B Output Support HCMOS Technology The MC44724A and MC44725A are advanced Digital Video Encoders (DVE). They convert ITU-601/656 standard 4:2:2 Bit- Paralellel data into analog composite video, S-Video or analog component signals Y/Cb/Cr ...
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Assignment] 1 CVBS / CVBS / CVBS / Vdd Vdd ...
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Descriptions] PIN NAME I/O 1 CVBS/Cb CVBS/Cb CVBS/Cb/B1Vdd Y/G 1Vdd 7 C/Cr C/Cr C/Cr/R 1Vdd 10 DAVss 11 ...
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Diagram] DVdd DVss H,V Y DVIA [ demux DVIB [ A/B_sel TP Clock ChipA Reset PAL/NTSC I2C/SPI chip-address This document contains information on a new product. Specifications and information herein are subject to ...
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Descriptions] Clock 27.0MHz. This signal on the clock pin needs to be active and stable for 5 cycles before the reset pin is de-asserted. Reset Procedure RESET is a level sensitive input pin. Driving the RESET pin low causes ...
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Input Data Format The input digital video is in accord with the ITU-R Rec.656 and SMPTE 125M standards two 8-bit or 16-bit multiplexed 4:2:2 ((CB,Y,CR)Y) data stream. Samples are latched on the rising edge of the clock signal. ...
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Fig 4 : Digital Input Timing(625/50 system) in Master Mode Hsync phase sub-address71[2:0] -3T delay +4T delay Hsync T 128T clock 8-bit input mode DVIA[7:0] INVALID 16-bit input mode DVIA[7:0] INVALID DVIB[7:0] INVALID Fig 5 : Sync Timing::525/60 Interlaced System ...
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Fig 6 : Sync Timing::625/50 Interlaced System in Master Mode Fsync Vsync Hsync CSYNC 621 622 623 624 625 Fsync Vsync Hsync CSYNC 309 310 311 312 Fig 7 : Sync Timing::525/60 Non-interlaced System in Master Mode Fsync Vsync Hsync ...
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Fig 10 : Sync Timing::525/60 Interlaced System in Slave Mode Odd field Fsync Vsync Hsync Internal Hsync reset counter CSYNC 3 Even field Fsync Vsync Hsync CSYNC For More Information On This Product, This document contains ...
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Fig 11 : Sync Timing::625/50 Interlaced System in Slave Mode Odd field Fsync Vsync Hsync Internal Hsync reset counter CSYNC 625 Even field Fsync Vsync Hsync CSYNC For More Information On This Product, This document contains information on a new ...
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Chroma / Luma Encoding The DVE de-multiplexes the 4:2:2 digital video data stream. The de-multiplexed Y or Luma samples are interpolated at the clock rate. Offset compensation is then added, next any VBI signals consisting of Closed-Caption, CGMS and WSS ...
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Fig 14 : Luminance Output Range IRE 670 100 620 89 540 70 490 7.5 232 0 56 -40 Analog Y output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup Off IRE 670 100 620 89 ...
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Fig 15 : Chrominance Output Range 222 146 128 34 16 Digital Cr-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar IRE -20 -45 -59 -63 IRE 21.5 0 -21.5 -48 -6 ...
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IRE 670 100 620 89 540 70 490 59 412 41 362 30 11 232 7.5 200 0 -40 12 Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup On IRE -20 -45 -59 ...
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IRE 670 100 620 89 540 70 490 59 412 41 362 30 11 232 0 -43 44 Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup Off IRE -20 -45 -59 -63 Digital ...
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Fig 18 : RGB Output Range for 525/60 system ( Sync On ) IRE 670 100 232 7.5 200 0 -40 12 Analog R output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On IRE 670 100 232 7.5 ...
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Fig 19 : RGB Output Range for 625/50 system ( Sync On ) IRE 670 100 232 0 -43 44 Analog R output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off IRE 670 100 232 0 -43 44 ...
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Fig 20 : RGB Output Range for 525/60 system ( Sync Off ) IRE 940 100 64 0 Analog R output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On IRE 940 100 64 0 Analog G output ...
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Fig 21 : RGB Output Range for 625/50 system ( Sync Off ) IRE 940 100 64 0 Analog R output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On IRE 940 100 64 0 Analog G output ...
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Copy Generation Management System (CGMS) Encoding CGMS signals can be encoded by the DVE onto output video line 20 (525 / 60 for Japan). CGMS identification signals also identify and control the TV screen presentation mode - wide screen, letter ...
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Serial Control Bus Control of the DVE device is accomplished through the I2C-Bus or 4-wired SPI serial bus. In I2C mode, pins SDA and SCL are the respective data and clock signals. Device address can be 40(hex)/41(hex) or 1E(hex)/1F(hex) . ...
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Fig 22-a : I2C-BUS Interface Write operation Timing SCL SDA MSB Start chip address(write) SCL SDA MSB Data 1 Fig 22-b : I2C-BUS Interface Read operation Timing SCL ...
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Fig 23-a : SPI-BUS Interface Write operation Timing SEL SCK MSB (Don't MSB care) Start Write Command SEL SCK MSB SO D7 ...
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Fig 23-b : SPI-BUS Interface Read operation Timing SEL SCK MSB (Don't MSB care) Start Write Command SEL SCK MSB x x ...
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Maximum Ratings DC Supply Voltage Input Voltage, All Inputs Output Voltage, All Outputs DC Output Current, per Pin Power Dissipation Storage Temperature Electrical Characteristics Characteristic Power Supply Voltage(Analog Blocks) DAVDD Power Supply Voltage(Digital Blocks) DVDD Supply Current(Analog Blocks) Supply ...
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Clock Blocks Characteristics Characteristic Clock Rate Clock Duty Cycle Digital Blocks Electrical Characteristics(Power Supply 3.3V,Ta= Characteristics Input Voltage HIGH LOW Output Voltage HIGH (2.0mA) LOW Input Leakage Current Hi-Z Leakage Current Input Capacitance Load Capacitance Data ...
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Slave Address 40(hex)/41(hex) or 1E(hex)/1F(hex)] <I2C-Bus Format> WRITE MODE S Slave Address A Sub Address 40(hex) or 1E(hex) if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed S Start condition Slave Address 40(hex) ...
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Format> WRITE MODE S Write Command Sub Address 40(hex) or 1E(hex) if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed S Chip select Lo) Write Command 40(hex) or ...
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Mapping and Description] Sub-address 6E : Y/CbCr mode setup (write) MSB - Register 6E default : 0000_0000(bin) M2/Beta Y mode CbCr gain Sub-address 6F : Interpolation Filter Switch (write) MSB - Register 6F default : 0000_0000(bin) Y Fil mode ...
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Sub-address 70 : Variable I/O Switch (write/read) MSB self-SW bs-off Register 70 default : 0000_0001(bin off : color burst control switch On/Off self - SW : internal self H/V counter reset switch On / Off color bar select ...
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Sub-address 71 : Sync control (write/read) MSB non-inter VBI SW Register 71 default : 0000_0100(bin) non-inter : non-interlaced mode select VBI SW : vertical blanking information signal input control switch on 48 pin h-polarity : polarity of Hsync v-polarity : ...
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Sub-address 72 : PAL/NTSC setup (write / read) MSB phase-set TEST Register 72 default : 0000_1000(bin) NTSC (If "PAL/NTSC" pin is LOW level) phase-set : color sub-carrier phase synchronization TEST : for test, should be "0" C/Fsync/VBI : Input/Output switch ...
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Sub-address 73: Vertical Blanking Information Luma (Y) Level (write only) MSB Register default : 1000_0000(bin) Sub-address 74: Burst Chroma (U) Level (write only) MSB Register default : 77(dec) (NTSC) Sub-address 75: Burst Chroma (V) ...
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Sub-address 76 : DAC set 1 signal control (write only) MSB Cr Register 76 default : 0000_0000(bin Cr/Cb signal control (Data path enable) Cb Luma : Luminance control (Data path enable) dac 1pin : D/A converter (1) output ...
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Sub-address 78~79 : Sub-carrier phase control (write only) MSB sc-ph9 Register 78 default : 0000_0000(bin) MSB - Register 79 default : 0000_0000(bin) sc-ph9 : sub-carrier phase control sc-ph8 sc-ph7 sc-ph6 sc-ph5 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0 For More Information On ...
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Sub-address 7A : Hsync delay control (write only) MSB H-delay10 H-delay9 H-delay8 H-delay7 Register 7A default : 0000_0000(bin) h-delay10 : delay on Hsync with reference to DVIA/DVIB data h-delay9 h-delay8 h-delay7 h-delay6 h-delay5 h-delay4 h-delay3 Note : this h-delay can ...
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Sub-address 7C : signal control 3(write only) MSB Ysync R/B sync Register 7C default : 0000_0000(bin) Y sync : Y sync Signal On/Off (Y/Cb/Cr mode only) R/B sync : R/B sync signal On/Off G sync : G sync signal On/Off ...
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Sub-address 7D~7E : Vsync delay control (write only) MSB V-delay7 V-delay6 V-delay5 V-delay4 Register 7D default : 0000_0000(bin) MSB - Register 7E default : 0000_0000(bin) V-delay9 : delay on Vsync with reference to DVIA/DVIB data in slave mode V-delay8 V-delay7 ...
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Sub-address 80~82: CGMS characters for Field1(Line20)/Field2(Line283) (write only) MSB Register 80 cgms7 b8 MSB Register 81 cgms15 b16 MSB Register 82 XX 70IRE 0IRE -40IRE Sub-address 80~81: WSS characters for Line23 (write only) MSB Register 80 wss7 b8 MSB Register ...
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Sub-address 83~84 :closed caption characters/extended data for Field1(Line21) (write) First byte to Encode MSB Register 83 ccp118 ccb117 parity Second byte to Encode MSB ccp128 ccb127 Register 84 parity Sub-address 85~86 :closed cation character/extended data for Field2(Line284) First byte to ...
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Sub-address 87 :Closed caption/CGMS MSB CC2_flag CC1_flag CC_null Register 87 CC2_flag : Closed Caption Status Flag for field2/field1 ( Read only) CC1_flag 0 : Automatically set to " 1 " when 2-byte Closed NOT work " 1 ...
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I2C-BUS Slave Receiver Sub-address map 70h:[7] burst control (default 0:on) [6] self counter reset switch (default 0:off) [5] color bar select (default 0:Luma 100% Chroma 75%) [4] vertical blanking switch(default 0:off) [3] 48 pin output mode select (Csync:1, Flame sync:0) ...
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Application Diagram 1 ] CVBS 180 0.01uF Y 47uF 180 0.01uF 47uF 180 C 47uF 0.01uF 2k 1.8K 47uF 1k 0.01uF 0.01uF 1. 0.01uF For More Information On This Product, This document contains information on a new ...
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Application Diagram 2 ] DVdd 47uF CVBS 180 0.01uF Y 47uF 180 0.01uF 47uF C 180 47uF 0.01uF 2k 1.8K 47uF 1k 0.01uF 0.01uF 1. 0.01uF For More Information On This Product, This document contains information on ...
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Package RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on ...