ADV7305AKST Analog Devices Inc, ADV7305AKST Datasheet - Page 29

• Manufacturer Part Number: ADV7305AKST
• Description: IC ENCODER VIDEO 14BIT 64LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7305AKST

• Applications: DVD, SD/HD
• Voltage - Supply, Analog: 2.5V
• Voltage - Supply, Digital: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INPUT AND OUTPUT CONFIGURATION
STANDARD DEFINITION ONLY
The 8- or 10-bit multiplexed input data is input on Pins S9–S0,
with S0 being the LSB in 10-bit Input Mode. For 8-bit Input
Mode, the data is input on Pins S9–S2. ITU-R.BT601/ITU-
R.BT656 input standards are supported. In 16-bit Input Mode,
the Y pixel data is input on Pins S9–S2 and CrCb data on
Pins Y9–Y2. In 20-bit Input Mode, the Y pixel data is input on
S9–S0 and CrCb pixel data on Pins Y9–Y0. The 27 MHz clock
input must be input on Pin CLKIN_A. Input sync signals are
optional and are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.
PROGRESSIVE SCAN ONLY OR HDTV ONLY
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4 format. In 4:2:2 Input Mode, the
Y data is input on Pins Y9–Y0 and the CrCb data on Pins C9–C0.
In 4:4:4 Input Mode, Y data is input on Pins Y9–Y0, Cb data
on Pins C9–C0, and Cr data on Pins S9–S0. If the YCrCb data
does not conform to SMPTE293M (525 p), ITU-R.BT1358M
(625 p), SMPTE274M (1080 i), SMPTE296M (720 p), or
BTA-T1004, the Async Timing Mode must be used. RGB data
can only be input in 4:4:4 format in PS Input Mode only, or
HDTV Input Mode only, when HD RGB input is enabled. G
data is input on Pins Y9–Y0, R data on S9–S0, and B data on
Pins C9–C0. The clock signal must be input on Pin CLKIN_A.
Synchronization signals are optional and are input on Pins
P_VSYNC, P_HSYNC, and P_BLANK.
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
YCrCb PS, HDTV, or any other HD data must be input in 4:2:2
format. In 4:2:2 Input Mode, the Y data is input on Pins Y9–Y0
and the CrCb data on C9–C0. If PS 4:2:2 data is interleaved onto a
single 10-bit bus, Pins Y9–Y0 are used for the Input Port. The
interleaved data is to be input at 27 MHz in setting the Input Mode
REV. A
Figure 20. Standard Definition Only Input Mode
Figure 21. Progressive Scan Only Input Mode
DECODER
PROGRESSIVE
INTERLACED
MPEG2
DECODER
YCrCb
MPEG2
TO
YCrCb
27MHz
27MHz
10
Cr
Cb
Y
3
10
10
10
3
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S9–S0
ADV7304A/
ADV7305A
ADV7304A/
CLKIN_A
S9–S0
C9–C0
Y9–Y0
P_VSYNC
P_HSYNC
P_BLANK
ADV7305A
–29–
Register at Address 01h accordingly. If the YCrCb data does not
conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p),
SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004,
the Async Timing Mode must be used.
The 8- or 10-bit standard definition data must be compliant to
ITU-R.BT601/ITU-R.BT656 in 4:2:2 format. Standard definition
data is input on Pins S9–S0, with S0 being the LSB. Using 8-bit input
format, the data is input on Pins S9–S2. The clock input for SD must
be input on CLKIN_A, and the clock input for HD must be input
on CLKIN_B. Synchronization signals are optional. SD syncs are
input on Pins S_VSYNC, S_HSYNC, and S_BLANK; the
HD syncs on Pins P_VSYNC, P_HSYNC, and P_BLANK.
If in Simultaneous Input Mode the two clock phases differ by less
than 9.25 ns or more than 27.75 ns, the Clock Align Bit must be
set accordingly. This also applies if the Pixel Align Bit is set. If
the application uses the same clock source for both SD and PS,
the Clock Align Bit must be set since the phase difference
between both inputs is less than 9.25 ns.
Figure 22. Simultaneous Progressive Scan and SD Input
Figure 24. Clock Phase with Two Input Clocks
Figure 23. Simultaneous HDTV and SD Input
t
t
DELAY
DELAY
PROGRESSIVE
DECODER
9.25ns OR
27.75ns
INTERLACED
MPEG2
YCrCb
DECODER
DECODER
SDTV
HDTV
TO
1080 i
720 p

ADV7304A/ADV7305A
YCrCb
CrCb
Y
74MHz
27MHz
27MHz
CrCb
Y
27MHz
8
8
8
3
3
10
10
10
3
3
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S9–S2
C9–C2
Y9–Y2
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
ADV7304A/
ADV7305A
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S9–S0
C9–C0
Y9–Y0
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
ADV7304A/
ADV7305A