ADV7173KSTZ Analog Devices Inc, ADV7173KSTZ Datasheet
ADV7173KSTZ
Specifications of ADV7173KSTZ
Available stocks
Related parts for ADV7173KSTZ
ADV7173KSTZ Summary of contents
Page 1
NOTES This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. 1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). 2 The Macrovision anticopy process is licensed ...
Page 2
ADV7172/ADV7173 CSO_HSO VSO CLAMP CLOCK PAL NTSC HSYNC FIELD/ VIDEO TIMING VSYNC GENERATOR BLANK RESET TTX TELETEXT INSERTION BLOCK TTXREQ YCrCb 4:2 4:4:4 COLOR YUV INTER- DATA 8 MATRIX POLATOR ...
Page 3
SPECIFICATIONS ( SPECIFICATIONS unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) 3 Integral Nonlinearity 3 Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input ...
Page 4
ADV7172/ADV7173–SPECIFICATIONS (V AA 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current ...
Page 5
V DYNAMIC SPECIFICATIONS Parameter 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 Differential Gain 3, 4 Differential Phase 3, 4 SNR (Pedestal SNR (Pedestal SNR (Ramp SNR (Ramp Hue ...
Page 6
ADV7172/ADV7173 5 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, ...
Page 7
V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
Page 8
ADV7172/ADV7173 SDATA SCLOCK CLOCK HSYNC, CONTROL FIELD/VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, FIELD/VSYNC, CONTROL BLANK, O/PS CSO_HSO, VSO, CLAMP TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES DAC Average Current Consumption DAC ...
Page 9
ABSOLUTE MAXIMUM RATINGS V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
ADV7172/ADV7173 Mnemonic Input/Output P7–P0 I CLOCK I HSYNC I/O FIELD/VSYNC I/O BLANK I/O SCRESET/RTC I V I/O REF R I SET1 R I SET2 COMP1 O COMP2 O DAC A O DAC B O DAC C O DAC D O ...
Page 11
INTERNAL FILTER RESPONSE The Y Filter supports several different frequency responses, including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response and a QCIF response. The UV ...
Page 12
ADV7172/ADV7173 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 ...
Page 13
FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 ...
Page 14
ADV7172/ADV7173 –1 –2 – FREQUENCY – MHz COLOR BAR GENERATION The ADV7172/ADV7173 can be configured to generate 100/ 7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for PAL. These ...
Page 15
YUV LEVELS This functionality is under the control of Mode Register 5, Bits 2–0. Bit 0 (MR50) allows the ADV7172/ADV7173 to output SMPTE levels on the Y output when configured in NTSC mode, and Betacam levels on the Y output ...
Page 16
ADV7172/ADV7173 COMPOSITE VIDEO e.g., VCR OR CABLE H/LTRANSITION COUNT START LOW 14 BITS 128 RESERVED 13 RTC TIME SLOT: 01 ADV7172/ADV7173 NOTES 1 F PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER ...
Page 17
Mode 0 (CCIR–656): Master Option (Timing Register 0 TR0 = The ADV7172/ADV7173 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes ...
Page 18
ADV7172/ADV7173 ANALOG VIDEO Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7172/ADV7173 accepts horizontal SYNC and Odd/ Even FIELD signals. A ...
Page 19
DISPLAY 622 623 624 HSYNC BLANK FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC BLANK FIELD ODD FIELD Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = ...
Page 20
ADV7172/ADV7173 Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode the ADV7172/ADV7173 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and ...
Page 21
Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = this mode the ADV7172/ADV7173 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and ...
Page 22
ADV7172/ADV7173 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7172/ADV7173 accepts or generates horizontal SYNC ...
Page 23
POWER-ON RESET After power-up necessary to execute a reset operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port such that the pixel inputs P7–P0 are not ...
Page 24
ADV7172/ADV7173 EXAMPLE: NTSC 525 1 OUTPUT VIDEO CSO HSO VSO CSO, HSO, AND VSO OUTPUTS The ADV7172/ADV7173 supports three timing signals, CSO (composite sync signal), HSO (horizontal sync signal) and VSO (vertical sync signal). These output TTL signals are aligned ...
Page 25
The ADV7172/ADV7173 acts as a standard slave device on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the ...
Page 26
ADV7172/ADV7173 Subaddress Register (SR7–SR0) The communications register is an 8-bit write-only register. After the part has been accessed over the bus and a read/write opera- tion is selected, the subaddress is set up. The subaddress register determines to/from which register ...
Page 27
MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 44 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION Output Video Standard Selection (MR01–MR00) These bits are used to set up the encoder mode. ...
Page 28
ADV7172/ADV7173 MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4–SR0) = 02H) Mode Register 8-bit-wide register. Figure 46 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION RGB/YUV Control (MR20) This bit enables the ...
Page 29
MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Mode Register 8-bit-wide register. Figure 47 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR31–MR30) This bit is read-only and ...
Page 30
ADV7172/ADV7173 MODE REGISTER 4 MR4 (MR47–MR40) (Address (SR4–SR0) = 04H) Mode Register 8-bit wide register. Figure 48 shows the various operations under the control of Mode Register 4. MR4 BIT DESCRIPTION VSYNC_3H (MR40) When this bit is ...
Page 31
MODE REGISTER 5 MR5 (MR57–MR50) (Address (SR4-SR0) = 05H) Mode Register 8-bit-wide register. Figure 49 shows the various operations under the control of Mode Register 5. MR5 BIT DESCRIPTION Y-Level Control (MR50) This bit controls the Y ...
Page 32
ADV7172/ADV7173 MODE REGISTER 6 MR6 (MR67–MR60) (Address (SR4–SR0) = 06H) Mode Register 8-bit-wide register. Figure 50 shows the various operations under the control of Mode Register 6. MR6 BIT DESCRIPTION Power-Up Sleep Mode Control (MR60) After reset ...
Page 33
MODE REGISTER 7 MR7 (MR77–MR70) (Address (SR4–SR0) = 07H) Mode Register 8-bit-wide register. Figure 51 shows the various operations under the control of Mode Register 7. MR7 BIT DESCRIPTION Color Control Enable (MR70) This bit is used ...
Page 34
ADV7172/ADV7173 TIMING REGISTER 0 (TR07–TR00) (Address (SR4–SR0) = 0AH) Figure 52 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to. TR0 BIT DESCRIPTION Master/Slave Control (TR00) This ...
Page 35
TIMING REGISTER 1 (TR17–TR10) (Address (SR4–SR0) = 0BH) Timing Register 8-bit-wide register. Figure 53 shows the various operations under the control of Timing Register 1. This register can be read from as well writ- ten to. This ...
Page 36
ADV7172/ADV7173 SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0) (Address (SR4–SR0) = 0CH–0FH) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: Subcarrier Frequency Re gister Example: NTSC Mode, ...
Page 37
TELETEXT REQUEST CONTROL REGISTER TC07 (TC07–TC00) (Address (SR4–SR0) = 1CH) Teletext Control Register is an 8-bit-wide register. See Figure 59. TTXREQ Rising Edge Control (TC07–TC04) These bits control the position of the rising edge of TTXREQ. It can be programmed ...
Page 38
ADV7172/ADV7173 CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CGMS_WSS Register 8-bit-wide register. Figure 61 shows the operations under control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W15–C/W10) These bit locations are shared by CGMS ...
Page 39
COLOR CONTROL REGISTERS 2–1 (CC2–CC1) (Address (SR4–SR0) = 1EH–1FH) The color control registers are 8-bit-wide registers used to scale the U and V output levels. Figure 64 shows the operations under control of these registers. CC1 BIT DESCRIPTION Reserved (CC17–CC16) ...
Page 40
ADV7172/ADV7173 BRIGHTNESS CONTROL REGISTERS (BCR) (Address (SR5–SR0) = 21H) The brightness control register is an 8-bit-wide register which allows brightness control. Figure 66 shows the operation under control of this register. BCR BIT DESCRIPTION Reserved (BCR7–BCR5) A Logic “0” must ...
Page 41
BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7172/ADV7173 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed ...
Page 42
ADV7172/ADV7173 “UNUSED 4k INPUTS SHOULD BE RESET GROUNDED” 4 10k TTX TTXREQ 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER) POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP ...
Page 43
The ADV7172/ADV7173 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed ...
Page 44
ADV7172/ADV7173 COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7172/ADV7173 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control ...
Page 45
The ADV7172/ADV7173 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7172/ADV7173 is configured in PAL mode. The WSS data is 14 bits long, the ...
Page 46
ADV7172/ADV7173 Time the time needed by the ADV7172/ADV7173 to interpolate input data on TTX and insert it onto the CVBS or Y out- PD, = 10.2 µs after the leading edge of the horizontal signal. Time, TTX puts, ...
Page 47
NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mV (p-p) 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 6 PEAK COMPOSITE ...
Page 48
ADV7172/ADV7173 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (p-p) 650mV 299.3mV 0mV 100 IRE 0 IRE –40 IRE NTSC WAVEFORMS (WITHOUT PEDESTAL) PEAK COMPOSITE 1289.8mV REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL ...
Page 49
PAL WAVEFORMS 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 989.7mV 300mV (p-p) 650mV 317.2mV 0mV 1050.2mV 351.8mV 51mV ADV7172/ADV7173 PEAK COMPOSITE REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL PEAK CHROMA 672mV (p-p) BLANK/BLACK ...
Page 50
ADV7172/ADV7173 334mV 171mV BETACAM LEVEL 0mV 171mV 334mV 505mV 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV 232mV SMPTE LEVEL 118mV 0mV –118mV –232mV –350mV UV WAVEFORMS 505mV BETACAM LEVEL 0mV 467mV BETACAM LEVEL 0mV 350mV SMPTE LEVEL 0mV 505mV ...
Page 51
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7172/ADV7173, the filter shown below can be used. The plot of the filter characteristics is shown in Figure 93. An Output Filter is ...
Page 52
ADV7172/ADV7173 The ADV7172/ADV7173 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite/luma/chroma outputs with DACs D, E and ...
Page 53
PAL M (Continued 3.57561149 MHz) SC Address 12Hex Closed Captioning Ext Register 1 13Hex Closed Captioning Register 0 14Hex Closed Captioning Register 1 15Hex Pedestal Control Register 0 16Hex Pedestal Control Register 1 17Hex Pedestal Control Register 2 ...
Page 54
ADV7172/ADV7173 POWER ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 ...
Page 55
OPTIONAL DAC BUFFERING 0.6 0.4 0.2 0.0 0.2 L608 0.0 10.0 20.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 L575 0.0 10.0 20.0 APL NEEDS ...
Page 56
ADV7172/ADV7173 0.5 0.0 –0.5 L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0.00 V ...
Page 57
F2 L238 10.0 20.0 NOISE REDUCTION: 15.05dB APL = 44.7% PRECISION MODE OFF 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 ...
Page 58
ADV7172/ADV7173 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7. 75% 100 R 100% 75 ...
Page 59
OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.057 (1.45) 0.030 (0.75) 0.276 (7.0) BSC 0.030 (0.75) 0.053 (1.35) 0.018 (0.45) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) ...
Page 60
...