AD723ARUZ Analog Devices Inc, AD723ARUZ Datasheet - Page 10

• Manufacturer Part Number: AD723ARUZ
• Description: IC ENCODER RGB-NTSC/PAL 28-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of AD723ARUZ

• Applications: Cameras, Internet Appliances, Set-Top Boxes
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Screening Level: Industrial
• Package Type: TSSOP
• Pin Count: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD723
Current Mode Output Drivers
In order to deliver a full swing video signal from a supply voltage
as low as 2.7 V, the AD723 uses current mode output drivers.
Bright colors like fully saturated yellow can reach peak ampli-
tudes as high as 1.4 V when measured from the bottom of the
sync pulse. A conventional output driver, with series reverse
termination, would require a 2.8 V internal swing, or more.
However, a current mode output stage, like those used in many
D/A converters, can deliver current into a shunt reverse termi-
nated load with half the swing requirements. This approach
requires an additional resistor to set the analog gain, see Figure
3. A gain setting resistor of 150 Ω is used so that the full output
voltage swing can be developed across the parallel 75 Ω loads at
the output terminal, CV. This resistor is kept external since the
gain accuracy depends on using like resistors for RL and RSET.
The use of a shunt reverse termination resistor, as in Figure 3,
results in higher current consumption when compared to series
termination. To reduce the current in a current-mode output
stage to levels comparable to a traditional voltage-mode output
stage, active termination can be employed, see Figure 4. In this
case, a gain setting resistor of 300 Ω is used, enough to supply
the current needed to drive the remote 75 Ω termination. No
current flows across the 375 Ω resistor between the CV and
CVSET terminals in steady state. This is the preferred output
configuration mode.
INTERNAL CV
INTERNAL CV
SIGNAL
SIGNAL
–
+
–
+
CVSET
CVSET
RSET
RSET
300
150
1:4
1:4
375
RA
75
CV
RL
CV
REMOTE
REMOTE
AVDD1
AVDD1
LOAD
LOAD
75
75
The small signal resistance seen looking into the CV terminal
can be shown to be 75 Ω due to the action of the output driver
feedback loop. This is true from dc to high frequencies. At
frequencies approaching 100 MHz and beyond the output
impedance gets larger, as the bandwidth of the feedback loop
is reached, and then smaller as the effects of shunt capacitance
come into play (as they do in the standard termination mode as
well). With the wide loop bandwidth of the output drivers, the
output impedance is kept close to 75 Ω for frequencies well
beyond the bandwidth of RS-170 video signals. This ensures
proper reverse termination of reflections on the line.
A further step toward reducing power consumption in the AD723
involves self-power-down of unused outputs. For those times
when a user loads the composite video output or the S-video
outputs, but not both, power can be saved by shutting down the
unloaded channel. The AD723 accomplishes this by periodically
checking for the presence of a load at the luma (Y) and compos-
ite video (CV) outputs. If an external load is added or removed
to either port the driver is turned on and off accordingly. The
chroma output (C) is turned on and off with luma (Y).
Load Check and TV Presence Detection
The provision for self-power-down of unused outputs just de-
scribed, is actually part of a more comprehensive load-checking
system. The AD723 is capable of checking for a load while in
several different states of operation, and is also capable of
reporting the presence of a load through the TVDET pin.
Awake-Mode Load Checking
When CE is high and an output driver is active, the continuing
presence of the load is verified by comparing the dc level at the
output to an internal reference. If the load is removed then the
voltage on the output pin (CV or Y) will become twice as high,
for standard termination, or even higher for active termination.
When CE is held high this checking is performed once at the
beginning of every 64th field of video (approximately once per
second), just after the first vertical sync pulse. If the absence of
a load is detected, the TVDET flag goes low for that output
and that output stage is turned off. Load checking is shown
in Figure 5. R, G, and B inputs should remain constant dur-
ing this interval.
Sleep-Mode Load Checking
When CE is high and an output driver is not active (i.e., sleep
mode), the AD723 needs to check for the addition of a new
load to the output. Rather than power up the output stage, a
special test current can be applied to compare the impedances
on the CV and CVSET pins (or Y and YSET) instead. This is
referred to as sleep-mode load checking. Since a small test cur-
rent is applied, there is little draw on the power supply to cause
interference with other, possibly active, outputs. This check is also
made at the beginning of every 64th field of video, just after the
first vertical sync pulse. If a load is detected, the output stage is
activated and the TVDET flag is raised high.