M28W640FSU70ZA6 Micron Technology Inc, M28W640FSU70ZA6 Datasheet
M28W640FSU70ZA6
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M28W640FSU70ZA6 Summary of contents
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... M28W320FST M28W320FSB M28W320FSU M28W640FST M28W640FSB M28W640FSU 3 V supply, Boot Block and Uniform Block, Secure Flash memories Features Supply voltage – 2 3.6 V core supply voltage DD – 2 3.6 V Input/Output voltage DDQ – Fast Program voltage (optional) PP Access time Programming time: – 10 µs typical – ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Block Protection Status (Bit 7.8 Reserved (Bit Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Appendix B Common Flash Interface (CFI Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Appendix D Command Interface and Program/Erase Controller state . . . . . . . 72 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Contents 3/76 ...
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List of tables List of tables Table 1. M28W320FS and M28W640FS memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M28WxxxFS, M28WxxxFSU List of figures Figure 1. M28W320FS logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Blocks starting from the bottom. Refer to detailed description of the devices memory architecture and map. The M28W320FSU and M28W640FSU are uniform block Flash memories. They are divided into thirty-two and sixty-four 64-KWord Uniform blocks, respectively. Refer to detailed description of the devices memory architecture and map. ...
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M28WxxxFS, M28WxxxFSU Program and Erase commands are written to the Command Interface of the memory. An on- chip Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can ...
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Description Figure 1. M28W320FS logic diagram Figure 2. M28W640FS logic diagram 8/ DDQ A0-A20 W E M28W320FST M28W320FSB SSQ DDQ A0-A21 W E ...
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M28WxxxFS, M28WxxxFSU Figure 3. M28W320FSU logic diagram Figure 4. M28W640FSU logic diagram DDQ A0-A20 W E M28W320FSU SSQ DDQ A0-A21 W E M28W640FSU ...
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Description Figure 5. TBGA64 connections (top view through package DQ8 The above figure gives the TBGA connections for the M28W640FST, M28W640FSB and M28W640FSU. ...
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M28WxxxFS, M28WxxxFSU Figure 6. TFBGA47 connections (top view through package A13 B A14 C A15 D A16 E V DDQ The two V balls (balls A5 and E1) must be connected to the power ...
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Description Figure 7. M28W320FST and M28W320FSB block addresses M28W320FST Top Boot Block Addresses 1FFFFF 4 KWords 1FF000 1F8FFF 4 KWords 1F8000 1F7FFF 32 KWords 1F0000 00FFFF 32 KWords 008000 007FFF 32 KWords 000000 1. Also see Appendix Figure 8. M28W640FST ...
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M28WxxxFS, M28WxxxFSU Figure 9. M28W320FSU and M28W640FSU block addresses M28W320FSU Block Addresses 1FFFFFh 64 KWords 1F0000h 1EFFFFh 64 KWords 1E0000h 01FFFFh 64 KWords 010000h 00FFFFh 64 KWords 000000h 1. Also see Appendix Figure 10. Protection Register memory map 3FFFFFh 3F0000h ...
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Signal descriptions 2 Signal descriptions See Figure 1, Figure Signal names, for a brief overview of the signals connected to this devices. 2.1 Address Inputs The Address Inputs select the cells in the memory array to access during Bus Read ...
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M28WxxxFS, M28WxxxFSU 2.7 V Supply Voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (Read, Program and Erase). 2.8 V Supply Voltage DDQ V ...
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... Read Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must should be used to enable the device. Output Enable should be used to gate data onto the output ...
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M28WxxxFS, M28WxxxFSU 3.5 Automatic Standby Automatic Standby provides a low power consumption state during Read mode. Following a read operation, the device enters Automatic Standby after 150ns of bus inactivity even if Chip Enable is Low, V will still output ...
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Hardware Protection 4 Hardware Protection All devices feature hardware protection. Refer to description of these signals. All the memory blocks are protected from program or erase operations when V equal PPLK 5 Security features The M28W320FS, M28W640FS, ...
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M28WxxxFS, M28WxxxFSU 6 Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution ...
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... FFh 6.4 Read CFI Query command The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area, allowing programming equipment or applications to automatically match their interface to the characteristics of the device. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area ...
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M28WxxxFS, M28WxxxFSU 6.5 Block Erase command The Block Erase command can be used to erase a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is ...
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Command Interface 6.7 Double Word Program command This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Three bus write cycles are necessary ...
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M28WxxxFS, M28WxxxFSU 6.10 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Erase operation. One bus write cycle is required to issue the Program/Erase command and pause the Program/Erase controller. During Program/Erase Suspend the Command ...
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Command Interface Table 5. Commands Commands 1st Cycle Op. Add Data Read Memory 1+ Write X Array Read Status 1+ Write X Register Read Electronic 1+ Write X Signature Read CFI 1+ Write X Query Erase 2 Write X Program ...
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M28WxxxFS, M28WxxxFSU Table 6. Read Electronic Signature (1) Code Device Manufacture All Code Device Code M28W320FST M28W320FSB M28W640FST Device Code M28W640FSB M28W320FSU M28W640FSU Addresses range from A0 to A20 for the M28W320FS and ...
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Command Interface Table 8. Program/Erase times and endurance cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Block Program (M28W320FS, M28W640FS) Parameter Block Program Block Program (M28W320FSU, M28W640FSU) Main Block Block Erase Erase (M28W320FS, Parameter M28W640FS) ...
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M28WxxxFS, M28WxxxFSU 7 Status Register The Status Register provides information on the current or previous Program or Erase operation. The various bits convey information and errors on the operation. To read the Status register the Read Status Register command can ...
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Status Register 7.3 Erase Status (Bit 5) The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly. When the Erase Status bit is High (set to ‘1’), the ...
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M28WxxxFS, M28WxxxFSU 7.7 Block Protection Status (Bit 1) The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit ...
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Maximum rating 8 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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M28WxxxFS, M28WxxxFSU 9 DC and ac parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics Tables that follow, are derived from tests performed ...
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DC and ac parameters Figure 11. AC measurement load circuit Table 13. Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. 32/76 V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ ...
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M28WxxxFS, M28WxxxFSU Table 14. DC characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) DD Supply Current (Standby or I DD1 Automatic Stand-by) I Supply Current (Reset) DD2 I Supply Current (Program) ...
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DC and ac parameters Figure 12. Read ac waveforms A0-A20/A21 ( DQ0-DQ15 ADDR. VALID CHIP ENABLE 1. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and M28W640FSU. ...
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M28WxxxFS, M28WxxxFSU Figure 13. Write ac waveforms, Write Enable controlled 1. Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and M28W640FSU. DC and ac parameters 35/76 ...
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DC and ac parameters Table 16. Write ac characteristics, Write Enable controlled Symbol Alt t t AVAV AVWH DVWH ELWL CS t ELQV (1)(2) t QVVPL ( VPHWH VPS ...
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M28WxxxFS, M28WxxxFSU Figure 14. Write ac waveforms, Chip Enable controlled Note:1.Addresses range from A0 to A20 for the M28W320FS and M28W320FSU, and from A0 to A21 for the M29W640FS and M28W640FSU. DC and ac parameters 37/76 ...
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DC and ac parameters Table 17. Write ac characteristics, Chip Enable controlled Symbol Alt t t AVAV AVEH DVEH EHAX EHDX EHEL CPH t EHGL ...
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M28WxxxFS, M28WxxxFSU Figure 15. Power-Up and Reset ac waveforms tVDHPH VDD, VDDQ Table 18. Power-Up and Reset ac characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, Chip Enable Low, t PHEL Output Enable ...
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Package mechanical 10 Package mechanical Figure 16. TBGA64 - 10 × 13 active ball array pitch, bottom view package outline E BALL "A1" 1. Drawing is not to scale. Table 19. TBGA64 - 10 × 13 active ball ...
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M28WxxxFS, M28WxxxFSU Figure 17. TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, view through package E BALL "A1" 1. Drawing is not to scale. Table 20. TFBGA47 - 8 × 6 active ball array, 0.75 mm pitch, ...
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... Device type M28 Operating voltage 2 3 Density 320F = 32 Mbit (2 Mb x16) 640F = 64 Mbit (4 Mb x16) Security S = Krypto™ Flash Memory block organization T = Top boot B = Bottom boot U = Uniform Speed 70 = 70ns Package ZA = TBGA64:10 × pitch ZB = TFBGA47, 6.39 × 6.37 mm, 0.75 mm pitch Temperature Range ° ...
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M28WxxxFS, M28WxxxFSU Appendix A Block address tables Table 22. Top Boot Block addresses, M28W320FST # ...
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Block address tables Table 22. Top Boot Block addresses, M28W320FST (continued ...
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M28WxxxFS, M28WxxxFSU Table 23. Bottom Boot Block addresses, M28W320FSB # ...
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Block address tables Table 23. Bottom Boot Block addresses, M28W320FSB (continued ...
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M28WxxxFS, M28WxxxFSU Table 24. Top Boot Block Addresses, M28W640FST # ...
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Block address tables Table 24. Top Boot Block Addresses, M28W640FST (continued ...
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M28WxxxFS, M28WxxxFSU Table 24. Top Boot Block Addresses, M28W640FST (continued ...
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Block address tables Table 24. Top Boot Block Addresses, M28W640FST (continued) # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 ...
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M28WxxxFS, M28WxxxFSU Table 25. Bottom Boot Block addresses, M28W640FSB # 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 ...
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Block address tables Table 25. Bottom Boot Block addresses, M28W640FSB (continued ...
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M28WxxxFS, M28WxxxFSU Table 25. Bottom Boot Block addresses, M28W640FSB (continued ...
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Block address tables Table 25. Bottom Boot Block addresses, M28W640FSB (continued ...
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M28WxxxFS, M28WxxxFSU Table 26. Block addresses, M28W320FSU Block Number ...
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Block address tables Table 27. Block addresses, M28W640FSU Block Number ...
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M28WxxxFS, M28WxxxFSU Table 27. Block addresses, M28W640FSU (continued) Block Number Block ...
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... Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary ...
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... Address for Primary Algorithm extended Query table (see Table 31) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (0000h means none exists) Address for Alternate Algorithm extended Query table (0000h means none exists) Common Flash Interface (CFI) Value ST Top Bottom Uniform "Q" "R" ...
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... Common Flash Interface (CFI) Table 30. CFI query system interface information Offset Data 1Bh 0027h 1Ch 0036h 1Dh 00B4h 1Eh 00C6h 1Fh 0004h 20h 0004h 21h 000Ah 22h 0000h 23h 0005h 24h 0005h 25h 0003h 26h 0000h 60/76 Description V Logic Supply Minimum Program/Erase or Write voltage ...
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... Data Description 0016h n Device Size = 2 in number of bytes 0017h 0001h Flash Device Interface Code description 0000h 0003h Maximum number of bytes in multi-byte program or page 0000h Number of Erase Block Regions within the device. 0001h It specifies the number of regions within the device containing contiguous Erase Blocks of the same size ...
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... Common Flash Interface (CFI) Table 31. Device geometry definition Offset Word Mode 2Dh 2Eh 2Fh 30h 31h to 34h 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 2Dh 2Eh 2Fh 30h 31h to 34h 62/76 Data ...
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... BCD value in 100mV V Supply Optimum Program/Erase voltage PP bit HEX value in volts bit BCD value in 100mV Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Common Flash Interface (CFI) Value "P" "R" "I" "1" "0" No ...
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... Common Flash Interface (CFI) Table 32. Primary algorithm-specific extended query table (continued) Offset Data ( 35h (P+F)h = 44h 0080h (P+10)h = 45h 0000h (P+11)h = 46h 0003h 0003h (P+12)h = 47h 0004h (P+13)h = 48h 1. See Table 29, offset 15 for P pointer definition. Table 33. Security code area Offset Data ...
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... Status check of b1 (Protected Block after a sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10 writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address) ; ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 66/76 double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1. quadruple_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x56) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; writeToFlash (addressToProgram3, dataToProgram3) ; writeToFlash (addressToProgram4, dataToProgram4) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... must be toggled*/ } while (status_register.b7 writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } { writeToFlash (any_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } AI03540b ...
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... YES YES End error is found, the Status Register must be cleared before further Program/Erase operations. erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... must be toggled*/ } while (status_register.b7 writeToFlash (any_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } { writeToFlash (any_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume erase*/ } AI03542b ...
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... YES End 1. Status check of b1 (Protected Block after a sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address) ; ...
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Command Interface and Program/Erase Controller state Appendix D Command Interface and Program/Erase Controller state Table 34. Write State Machine Current/Next, sheet Data Current SR Read When State bit 7 Array Read (FFh) Read Read “1” Array Array ...
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M28WxxxFS, M28WxxxFSU Table 34. Write State Machine Current/Next, sheet Data Current SR Read When State bit 7 Array Read (FFh) Erase “0” Status (continue) Erase Sus Erase Sus “1” Status Read Read Sts Array Erase Sus Erase ...
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Command Interface and Program/Erase Controller state Table 35. Write State Machine Current/Next, sheet Current State Read Array Read Status Read Elect.Sg. Read CFI Query Prot. Prog. Setup Prot. Prog. (continue) Prot. Prog. (complete) Prog. Setup Program (continue) ...
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M28WxxxFS, M28WxxxFSU 12 Revision history Table 36. Document revision history Date Revision 25-Oct-2005 21-Sep-2006 15-Dec-2006 Initial release. This datasheet is the merge of the M28WxxxFS datasheet (revision 2.0) concerning the M28W320FS and 1.0 M28W640FS, and of the M28WxxxFSU datasheet (revision ...
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any ...